公开(公告)号：DE102004031741A1

公开(公告)日：2006-01-26

申请号：DE102004031741

申请日：2004-06-30

Applicant: INFINEON TECHNOLOGIES AG

Inventor： HARTER JOHANN ,  SCHUSTER THOMAS

IPC: H01L21/336

Abstract: Provided is an integrated circuit including a transistor with a gate electrode. The gate electrode includes a polysilicon layer in contact with a gate dielectric layer separating the gate electrode and a semiconductor substrate that comprises an active region of the transistor. The gate electrode includes sidewall structures extending along lower portions of opposing sidewalls of the polysilicon layer, the lower portion being oriented to the semiconductor substrate. The gate electrode also includes a barrier layer. A first section of the barrier layer extends along an upper portion of the sidewall of the polysilicon layer, the upper portion being adjacent to the lower portion and facing away from the semiconductor substrate.

公开(公告)号：DE102004043857B3

公开(公告)日：2006-03-30

申请号：DE102004043857

申请日：2004-09-10

Applicant: INFINEON TECHNOLOGIES AG

Inventor： HARTER JOHANN ,  MUELLER WOLFGANG ,  BERGNER WOLFGANG ,  GRUENING ULRIKE VON SCHWERIN ,  SCHLOESSER TILL ,  WEIS ROLF

IPC: H01L27/108 ,  G11C11/404 ,  H01L21/8242

Abstract: Stack and trench memory cells are provided in a DRAM memory cell array. The stack and trench memory cells are arranged so as to form identical cell pairs each having a trench capacitor, a stack capacitor and a semiconductor fin, in which the active areas of two select transistors for addressing the trench and stack capacitors are formed. The semiconductor fins are arranged in succession in the longitudinal direction to form cell rows and in this arrangement are spaced apart from one another by in each case a trench capacitor. Respectively adjacent cell rows are separated from one another by trench isolator structures and are offset with respect to one another by half the length of a cell pair. The semiconductor fins are crossed by at least two active word lines, which are orthogonal with respect to the cell rows, for addressing the select transistors realized in the semiconductor fin.