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    Method for forming semiconductor device
    1.
    发明专利
    Method for forming semiconductor device 审中-公开
    形成半导体器件的方法

    公开(公告)号：JP2006295181A

    公开(公告)日：2006-10-26

    申请号：JP2006107761

    申请日：2006-04-10

    Applicant: Infineon Technologies Ag ,  インフィネオン テヒノロギーズ アーゲーInfineon TechnologiesAG

    Inventor： STORBECK OLAF ,  HAHN JENS ,  SCHMIDBAUER SVEN ,  FAUL JUERGEN ,  JAKUBOWSKI FRANK ,  SCHUSTER THOMAS

    IPC: H01L21/28 ,  H01L21/20 ,  H01L29/423 ,  H01L29/49 ,  H01L29/78

    CPC classification number: H01L21/265 ,  H01L21/28044 ,  H01L21/324 ,  H01L29/4925

    Abstract: PROBLEM TO BE SOLVED: To provide a method for forming a semiconductor device configured by a gate dielectric layer and an impurity semiconductor formed so as to achieve a small gate leak current or at least a suitable gate leak current. SOLUTION: The manufacturing method of a semiconductor includes a step of providing a substrate, a step of forming a dielectric layer on the substrate, a step of growing an amorphous semiconductor layer on the dielectric layer, a step of doping impurity in the amorphous semiconductor layer, and a step of forming a crystallized layer from the amorphous semiconductor by performing a high-temperature process on the amorphous layer. COPYRIGHT: (C)2007,JPO&INPIT

    Abstract translation: 要解决的问题：提供一种形成由栅介质层和杂质半导体构成的半导体器件的方法，其形成为实现小的漏极电流或至少合适的栅极漏电流。 解决方案：半导体的制造方法包括提供衬底的步骤，在衬底上形成电介质层的步骤，在电介质层上生长非晶半导体层的步骤，将掺杂杂质的步骤 非晶半导体层，以及通过对非晶层进行高温处理从非晶半导体形成结晶化层的工序。 版权所有（C）2007，JPO＆INPIT

    3.
    发明专利
    未知

    公开(公告)号：DE10356476B3

    公开(公告)日：2005-06-30

    申请号：DE10356476

    申请日：2003-12-03

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： AMON JUERGEN ,  FAUL JUERGEN ,  SCHUSTER THOMAS ,  MUELLER RALF ,  KIESLICH ALBRECHT ,  ALSMEIER JOHANN ,  OFFENBERG DIRK ,  GOLDBACH MATTHIAS

    IPC: H01L27/108 ,  H01L21/265 ,  H01L21/8242

    Abstract: A method fabricates a semiconductor structure having a plurality of memory cells that are provided in a semiconductor substrate of a first conductivity type and contains a plurality of planar selection transistors and a corresponding plurality of storage capacitors connected thereto. The selection transistors have respective first and second active regions of a second conductivity type. The first active regions are connected to the storage capacitors and the second active regions are connected to respective bit lines, and respective gate stacks, which are provided above the semiconductor substrate in a manner insulated by a gate dielectric. In this case, a single-sided halo doping is effected, and an excessive outdiffusion of the halo doping zones is prevented by introduction of a diffusion-inhibiting species.

    5.
    发明专利
    未知

    公开(公告)号：DE10157538A1

    公开(公告)日：2003-06-12

    申请号：DE10157538

    申请日：2001-11-23

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： SCHUSTER THOMAS ,  TOEBBEN DIRK

    IPC: H01L21/60 ,  H01L21/8242 ,  H01L29/78 ,  H01L21/336

    Abstract: A field effect transistor contains a gate stack with a first layer, preferably a polysilicon layer, on a gate oxide disposed on a substrate, and over the first layer, a second layer, preferably a silicide layer, is provided. Next to the gate electrode is a contact that is separated from the layers of the gate electrode by a layer containing silicon and a spacer layer. Therefore a recrystallization in the silicide layer at elevated temperatures is prevented, which would otherwise cause bulging of the silicide layer toward the contact. It thus prevents shorts between the gate electrode and the contact.

    6.
    发明专利
    未知

    公开(公告)号：DE10157538B4

    公开(公告)日：2006-05-11

    申请号：DE10157538

    申请日：2001-11-23

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： SCHUSTER THOMAS ,  TOEBBEN DIRK

    IPC: H01L29/78 ,  H01L21/336 ,  H01L21/60 ,  H01L21/8242

    Abstract: A field effect transistor contains a gate stack with a first layer, preferably a polysilicon layer, on a gate oxide disposed on a substrate, and over the first layer, a second layer, preferably a silicide layer, is provided. Next to the gate electrode is a contact that is separated from the layers of the gate electrode by a layer containing silicon and a spacer layer. Therefore a recrystallization in the silicide layer at elevated temperatures is prevented, which would otherwise cause bulging of the silicide layer toward the contact. It thus prevents shorts between the gate electrode and the contact.

    9.
    发明专利
    未知

    公开(公告)号：DE102004031741A1

    公开(公告)日：2006-01-26

    申请号：DE102004031741

    申请日：2004-06-30

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： HARTER JOHANN ,  SCHUSTER THOMAS

    IPC: H01L21/336

    Abstract: Provided is an integrated circuit including a transistor with a gate electrode. The gate electrode includes a polysilicon layer in contact with a gate dielectric layer separating the gate electrode and a semiconductor substrate that comprises an active region of the transistor. The gate electrode includes sidewall structures extending along lower portions of opposing sidewalls of the polysilicon layer, the lower portion being oriented to the semiconductor substrate. The gate electrode also includes a barrier layer. A first section of the barrier layer extends along an upper portion of the sidewall of the polysilicon layer, the upper portion being adjacent to the lower portion and facing away from the semiconductor substrate.

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