公开(公告)号：JP2007329489A

公开(公告)日：2007-12-20

申请号：JP2007176125

申请日：2007-07-04

Applicant: Infineon Technologies Ag ,  インフィニオン テクノロジーズ アクチエンゲゼルシャフトInfineon Technologies Ag

Inventor： ROESNER WOLFGANG ,  HOFMANN FRANZ ,  BERTAGNOLLI EMMERICH ,  GOEBEL BERND

IPC: H01L21/8234 ,  H01L29/78 ,  H01L21/336 ,  H01L21/8239 ,  H01L21/8242 ,  H01L21/8246 ,  H01L27/04 ,  H01L27/088 ,  H01L27/105 ,  H01L27/108 ,  H01L27/112

CPC classification number: H01L27/10876 ,  H01L27/1052 ,  H01L27/10823 ,  H01L27/112 ,  H01L27/11273

Abstract: PROBLEM TO BE SOLVED: To provide a high-density integrated circuit device by which a floating body effect of a transistor can be avoided.
SOLUTION: A vertical MOS transistor includes a series of layers SF, SF* arranged on a first conductive type substrate 1. The series of layers comprise a lower layer U for a first source/drain region, an intermediate layer M doped with a first conductive type to act as a channel region, and an upper layer O for a second source/drain region. A connection structure V doped with the first conductive type is arranged on a first surface of the series of layers SF, SF* to electrically connect the channel region to the substrate 1. A gate electrode of the transistor is arranged on a second surface of the series of layers SF, SF*. The connection structure V can be arranged between the series of layers SF, SF* and the same or another series of layers SF, SF*. The dimension of the connection structure V or the like can be a lithography dimension or less. The manufactured circuit is suitable for a storage cell arrangement.
COPYRIGHT: (C)2008,JPO&INPIT

Abstract translation: 要解决的问题：提供可以避免晶体管的浮体效应的高密度集成电路器件。 解决方案：垂直MOS晶体管包括布置在第一导电型衬底1上的一系列层SF，SF *。一系列层包括用于第一源/漏区的下层U，掺杂有 用作沟道区的第一导电类型和用于第二源极/漏极区的上层O。 掺杂有第一导电类型的连接结构V布置在一系列层SF，SF *的第一表面上，以将沟道区域电连接到衬底1.晶体管的栅极布置在第二表面上 系列SF，SF *。 连接结构V可以布置在一系列层SF，SF *和相同或另一系列层SF，SF *之间。 连接结构V等的尺寸可以是光刻尺寸或更小。 制造的电路适用于存储单元布置。 版权所有（C）2008，JPO＆INPIT

公开(公告)号：WO0248396A3

公开(公告)日：2003-09-04

申请号：PCT/DE0104719

申请日：2001-12-14

Applicant: INFINEON TECHNOLOGIES AG ,  HOFMANN FRANZ ,  LUYKEN RICHARD JOHANNES ,  STEIBL MARTIN ,  SCHINDLER-BAUER PETRA THERESIA

Inventor： HOFMANN FRANZ ,  LUYKEN RICHARD JOHANNES ,  STEIBL MARTIN ,  SCHINDLER-BAUER PETRA THERESIA

IPC: C12Q1/68

CPC classification number: C12Q1/6825

Abstract: The sensor for detecting macromolecular biomolecules comprises a radiation detector and a radiolucent adhesive layer, which is arranged above the radiosensitive side of the radiation detector and which is provided as to enable scavenger molecules to bind to the adhesive layer. The existence of macromolecular biomolecules, which are complementary or specific to the structure of the scavenger molecules, in the solution to be examined can be concluded based on the evaluation of radiation detector output signals.

Abstract translation: 用于检测生物分子的大分子所述传感器包括在所述strahlunsempfinlichen Strahlunsdetektorsstrahlunsdurchlässige粘合剂层的一侧上的辐射检测器和布置被形成为使得所述捕获分子可以附着到粘合剂层上。 基于输出信号的Ausertung Strahlunsdetektor-可以得出结论，待检查的，以在溶液中的捕获分子互补或特定高分子生物分子的结构的存在。

公开(公告)号：WO02074985A3

公开(公告)日：2003-05-08

申请号：PCT/DE0200868

申请日：2002-03-12

Applicant: INFINEON TECHNOLOGIES AG ,  HOFMANN FRANZ ,  LUYKEN RICHARD JOHANNES

Inventor： HOFMANN FRANZ ,  LUYKEN RICHARD JOHANNES

IPC: G01N33/53 ,  C12Q1/42 ,  C12Q1/44 ,  C12Q1/48 ,  C12Q1/68 ,  G01N27/02 ,  G01N33/543 ,  G01N33/566 ,  C12Q1/00 ,  G01N33/68

CPC classification number: G01N33/5438 ,  C12Q1/6825 ,  C12Q1/6837 ,  C12Q2565/543 ,  C12Q2565/607

Abstract: The invention relates to a method of detecting macromolecular biopolymers by means of an electrode arrangement that comprises a first and a second electrode. The inventive method is characterized by carrying out a first electrical measurement on the electrodes. In a further step, a solution to be examined, which may contain the macromolecular biopolymers to be detected, is contacted with the electrode arrangement. In another step, the macromolecular biopolymers to be detected that are contained it the solution to be examined are bound to the scavenger molecules on the first and on the second electrode and the electrode arrangement is contacted with a reagent to increase conductivity of the macromolecular biopolymers, said reagent binding to the macromolecular biopolymers and bestowing them with electroconductivity. A second electrical measurement is carried out on the electrodes and the macromolecular biopolymers are detected on the basis of the comparison of the results of the two electrical measurements on the electrodes.

Abstract translation: 在该方法中，电极组件被插入时，其具有第一和第二电极。 在该方法中，在所述电极的第一电进行测量。 在另一步骤中，要被检查的溶液被带入与所述电极组件，其中，待检测的溶液可以含有大分子生物聚合物接触。 在进一步的步骤中，在被检查溶液被束缚包含待检测的大分子生物聚合物以在第一和第二电极以及在电极组件中，捕捉分子被带入接触用试剂以增加大分子的生物聚合物的导电性，其结合到大分子生物聚合物 这赋予导电性。 随后，第二电测量是在所述电极进行和大分子生物聚合物被检测取决于在电极处的两个电测量结果的比较。

公开(公告)号：WO03014695A2

公开(公告)日：2003-02-20

申请号：PCT/DE0202706

申请日：2002-07-23

Applicant: INFINEON TECHNOLOGIES AG ,  HOFMANN FRANZ ,  LUYKEN RICHARD JOHANNES ,  SCHINDLER-BAUER PETRA THERESIA

Inventor： HOFMANN FRANZ ,  LUYKEN RICHARD JOHANNES ,  SCHINDLER-BAUER PETRA THERESIA

IPC: G01N33/53 ,  C12M1/00 ,  C12Q1/68 ,  G01N21/76 ,  G01N21/77 ,  G01N21/78 ,  G01N33/543 ,  G01N33/552 ,  G01N37/00 ,  G01N

CPC classification number: G01N33/552 ,  G01N21/76 ,  G01N33/54366 ,  G01N2021/7763 ,  G01N2223/413

Abstract: According to the inventive method, at least one unit is provided for immobilizing macromolecular biopolymers, said unit being incorporated in a substrate or applied to said substrate. The at least one immobilizing unit is provided with scavenger molecules. A sample which can contain the macromolecular biopolymers to be detected is then brought into contact with the at least one immobilizing unit. Macromolecular biopolymers contained in the sample are bound to the scavenger molecules. The production of a chemiluminescence signal is induced by means of a marking and the chemiluminescence signal is detected by a detection unit embodied in the substrate in the form of an integrated circuit, whereby the macromolecular biopolymers are detected.

Abstract translation: 在该方法中，至少一个单元用于固定被集成在一个衬底或沉积在衬底上的大分子生物聚合物。 所述至少一个固定单元设置有捕获分子。 可以被检测到的样品包括大分子生物聚合物，然后使其与所述至少一个固定单元接触。 样品中含有的高分子生物聚合物结合至捕捉分子。 通过标签的手段，化学发光信号的产生被激发，化学发光信号由配置为在衬底的集成电路检测单元，并由此大分子生物聚合物进行检测。

公开(公告)号：WO03088310A2

公开(公告)日：2003-10-23

申请号：PCT/DE0301281

申请日：2003-04-16

Applicant: INFINEON TECHNOLOGIES AG ,  HOFMANN FRANZ ,  LUYKEN RICHARD JOHANNES ,  ROESNER WOLFGANG ,  SPECHT MICHAEL ,  STAEDELE MARTIN

Inventor： HOFMANN FRANZ ,  LUYKEN RICHARD JOHANNES ,  ROESNER WOLFGANG ,  SPECHT MICHAEL ,  STAEDELE MARTIN

IPC: H01L29/06 ,  H01L21/02 ,  H01L21/20 ,  H01L21/265 ,  H01L21/336 ,  H01L21/762 ,  H01L21/8234 ,  H01L27/08 ,  H01L27/088 ,  H01L27/12 ,  H01L29/786 ,  H01L

CPC classification number: H01L21/76262 ,  H01L21/76251

Abstract: The invention relates to a substrate (600) which is provided with a support layer (501). An insulator layer (502) is applied to the support layer (501), comprising at least two areas having respectively different thicknesses. A semi-conductor layer (303) having an FD-area (304) and a PD-area (305) is applied to the surface of the insulating layer (502), comprising a planar surface. The planar surface is the surface which is opposite the insulating layer (502).

Abstract translation: 本发明提供一种基板（600），其包括载体层（501）。 其中的绝缘层（502）被施加，包括各自具有不同厚度的至少两个区域的载体层（501）上。 在绝缘体层的表面（502）是与FD区域（304）和PD区域（305）的半导体层（303）被施加，其具有平坦表面，所述平坦表面与所述表面的绝缘体层（502） 对面。

公开(公告)号：WO03067639A3

公开(公告)日：2003-10-16

申请号：PCT/DE0300183

申请日：2003-01-23

Applicant: INFINEON TECHNOLOGIES AG ,  HOFMANN FRANZ ,  LANDGRAF ERHARD ,  LUYKEN HANNES

Inventor： HOFMANN FRANZ ,  LANDGRAF ERHARD ,  LUYKEN HANNES

IPC: H01L21/8247 ,  H01L21/28 ,  H01L21/336 ,  H01L21/8246 ,  H01L27/115 ,  H01L29/423 ,  H01L29/788 ,  H01L29/792

CPC classification number: H01L27/11568 ,  H01L21/28282 ,  H01L27/115 ,  H01L29/66833 ,  H01L29/792

Abstract: The invention relates to NROM memory cells that are disposed in trenches that are etched into the semiconductor material. The memory layer composed of a nitride layer (3) that is interposed between two oxide layers (2, 4) is applied to the trench walls before the dopants for source and drain (7) are implanted. The implantation regions of source and drain are thus prevented from being damaged by the high temperature loads of the component during production of the memory layer as the respective dopant is introduced only later on. Polysilicon gate electrodes (5) are connected to word lines (11).

Abstract translation: 的NROM存储单元被布置在被蚀刻到半导体材料中的沟槽。 氧化物层之间的氮化物层（3）的存储层（2,4）的掺杂剂为源极和漏极（7）到被植入之前施加到坟墓壁。 以这种方式，实现了在所述存储层的制造部件的高温负荷不能与源和漏区的注入干扰，如在讨论的掺杂剂将只随后引入。 由多晶硅制成的栅电极（5）被连接到字线（11）。

公开(公告)号：WO02090573A3

公开(公告)日：2003-04-10

申请号：PCT/DE0201700

申请日：2002-05-10

Applicant: INFINEON TECHNOLOGIES AG ,  FREY ALEXANDER ,  HOFMANN FRANZ ,  LUYKEN RICHARD JOHANNES

Inventor： FREY ALEXANDER ,  HOFMANN FRANZ ,  LUYKEN RICHARD JOHANNES

IPC: C12Q1/00 ,  G01N33/543 ,  C12Q1/68

CPC classification number: C12Q1/00 ,  G01N33/54373 ,  G01N33/5438

Abstract: The biochip comprises a substrate, at least one sensor, arranged on or in the substrate and an electrically conducting permeation layer, arranged at a given, non-zero separation from the surface of the substrate, to which an electrical voltage may be applied. The biochip arrangement may be used, for example, as a DNA sensor, whereby a receptor molecule, immobilised on the sensor electrode, hybridises a DNA molecule and thus an electrical sensor signal which may be drawn from between sensor electrodes, is influenced in a characteristic manner.

Abstract translation: 生物芯片组件包括一基板，至少一个设置在上或在衬底传感器和导电渗透层，其从所述衬底的表面布置在预定的非零的距离，并且其中，电电压可以被施加到。 生物芯片布置是有用的，例如，通过固定的捕获分子的DNA传感器杂交的DNA分子上的传感器电极，因此所涉及的传感器电极之间，可移动的电传感器信号特征的影响。

公开(公告)号：WO03003472A2

公开(公告)日：2003-01-09

申请号：PCT/DE0202263

申请日：2002-06-20

Applicant: INFINEON TECHNOLOGIES AG ,  HOFMANN FRANZ ,  WILLER JOSEF

Inventor： HOFMANN FRANZ ,  WILLER JOSEF

IPC: G11C11/56 ,  G11C16/04 ,  H01L21/336 ,  H01L21/8246 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

CPC classification number: H01L27/11568 ,  G11C11/5671 ,  G11C16/0475 ,  H01L27/115 ,  H01L27/11553 ,  H01L29/66833 ,  H01L29/7923

Abstract: The invention relates to a transistor-arrangement (200) with a substrate (201) and a vertical transistor, comprising a first electrode area (204), a second electrode area (205) arranged essentially thereabove, a channel area (203) arranged therebetween, in addition to a gate-area (207) and a channel area (203) and an electrically insulating sequence of layers (206) arranged therebetween, whereby two spatially separate sections (208, 209) of the electrically insulating sequence of layers (206) act as charge carriers for storage purposes.

Abstract translation: 本发明涉及一种包括基片（201）和一个垂直晶体管，包括一个晶体管装置（200）：第一电极部分（204），一个第二电极部分（205）上面的基本布置和在它们之间的沟道区（203），和一个 栅极区域（207）相邻的所述沟道区（203）和在它们之间的电绝缘层序列（206），其中所述电绝缘层序列的两个空间上分开的部分（208，209）（206），每个用于存储电荷载体。

公开(公告)号：WO0137342A2

公开(公告)日：2001-05-25

申请号：PCT/DE0003982

申请日：2000-11-14

Applicant: INFINEON TECHNOLOGIES AG ,  HOFMANN FRANZ ,  RISCH LOTHAR ,  ROESNER WOLFGANG ,  SCHLOESSER TILL

Inventor： HOFMANN FRANZ ,  RISCH LOTHAR ,  ROESNER WOLFGANG ,  SCHLOESSER TILL

IPC: H01L21/336 ,  H01L21/8242 ,  H01L27/108 ,  H01L27/12 ,  H01L29/78 ,  H01L29/786 ,  H01L25/00

CPC classification number: H01L27/10864 ,  H01L27/10867 ,  H01L27/10891 ,  H01L27/1203

Abstract: The invention relates to a transistor that is provided with a first source/drain area (S/D1), a channel area (KA) adjacent thereto, a second source/drain area (S/D 2) adjacent thereto, a gate dielectric and a gate electrode. A first capacitor electrode (SP) of the capacitor is connected to the first source/drain area (S/D1). An insulating structure entirely surrounds an insulating area of the circuit arrangement. At least the first capacitor electrode (SP) and the first source/drain area (S/D1) are arranged in the insulating area. The second source/drain area (S/D2) and the second capacitor electrode of the capacitor are arranged outside the insulating area. The insulating structure prevents the first capacitor electrode (SP) from loosing charge through leaking currents between charging and discharging of the capacitor. A tunnel barrier (T) which is arranged in the channel area (KA) is part of the insulating structure. A capacitor dielectric (KD) that separates the first capacitor electrode (SP) from the second capacitor electrode is part of the insulating structure.

Abstract translation: 该晶体管的第一源极/漏极区（S / D1），其上的沟道区相邻的（KA），一个与其相邻的第二源极/漏极区（S / D2），栅极电介质和栅极电极。 所述电容器的第一电容器电极（SP）被连接到所述第一源极/漏极区（S / D1）。 绝缘结构完全围绕的电路的绝缘区域。 在至少所述第一电容器电极（SP）和所述第一源极的绝缘区/漏极区（S / D1）被布置，而第二源极/漏极区（S / D2）和所述电容器的第二电容器电极上的绝缘外 排列区域。 因为绝缘结构的电荷不会丢失由于从充电和放电电容器之间的第一电容器电极（SP）的漏电流。 在沟道区中的隧穿势垒（T），其设置（KA），是在绝缘结构的部分。 电容器电介质（KD），（SP）分离所述第二电容器电极的第一电容器电极，在绝缘结构的部分。

公开(公告)号：WO2004040644A3

公开(公告)日：2004-08-12

申请号：PCT/DE0303589

申请日：2003-10-29

Applicant: INFINEON TECHNOLOGIES AG ,  GRAHAM ANDREW ,  HOFMANN FRANZ ,  HOENLEIN WOLFGANG ,  KRETZ JOHANNES ,  KREUPL FRANZ ,  LANDGRAF ERHARD ,  LUYKEN RICHARD JOHANNES ,  ROESNER WOLFGANG ,  SCHULZ THOMAS ,  SPECHT MICHAEL

Inventor： GRAHAM ANDREW ,  HOFMANN FRANZ ,  HOENLEIN WOLFGANG ,  KRETZ JOHANNES ,  KREUPL FRANZ ,  LANDGRAF ERHARD ,  LUYKEN RICHARD JOHANNES ,  ROESNER WOLFGANG ,  SCHULZ THOMAS ,  SPECHT MICHAEL

IPC: G11C13/02 ,  H01L21/8242 ,  H01L27/108 ,  H01L51/00 ,  H01L51/05 ,  H01L51/30 ,  H01L21/8239 ,  H01L51/20

CPC classification number: G11C13/025 ,  B82Y10/00 ,  G11C13/0033 ,  G11C2213/16 ,  H01L27/10841 ,  H01L27/10864 ,  H01L27/10876 ,  H01L27/283 ,  H01L51/0048 ,  H01L51/0052 ,  H01L51/0512 ,  H01L51/057

Abstract: The invention relates to a memory cell, memory cell arrangement, structuring arrangement and method for production of a memory cell. The memory cell has a vertical gate transistor and a memory capacitor, whereby the vertical gate transistor comprises a semiconducting nanostructure, grown on at least part of the memory capacitor.

Abstract translation: 本发明涉及一种存储器单元，存储器单元阵列，纹理化装置和一种用于制造存储器单元的方法。 该存储单元有一个垂直的开关晶体管和存储电容器，所述具有半导体纳米结构垂直开关晶体管上生长至少存储电容器的一部分。