Patent search ap:("INFINEON TECHNOLOGIES AG") AND inv:"JOSIEK ANDREI" Page 1

1.

发明专利
Configuration of memory cells and a testing structure on a wafer has the cells as part of integrated circuits encasing the testing structure and a memory cell with connecting strip conductors. 未知

公开(公告)号：DE10211037A1

公开(公告)日：2003-06-26

申请号：DE10211037

申请日：2002-03-13

Applicant: INFINEON TECHNOLOGIES AG

Inventor： BARTHOLOMAEUS LARS , GRAF WERNER , JOSIEK ANDREI , WICHTENDAHL RALPH

IPC: G11C29/00 , G11C29/50 , H01L23/544 , H01L27/11 , H01L21/66

Abstract: Memory cells are part of two or more integrated circuits (ICs). A testing structure fits between the ICs and has a memory cell (250) with connecting strip conductors (201-206) running in a strip conductor surface of metal and each linking to doping areas (241,243-4,245-7) for transistors (Q1-Q6) via vertical contacts (V1-V6). An Independent claim is also included for a semiconductor disk with two or more integrated circuits set apart from each other and a testing structure between these integrated circuits.

Patent Agency Ranking