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    Method for processing structured surface
    1.
    发明专利
    Method for processing structured surface 审中-公开
    处理结构表面的方法

    公开(公告)号：JP2006216946A

    公开(公告)日：2006-08-17

    申请号：JP2006019743

    申请日：2006-01-27

    Applicant: Infineon Technologies Ag ,  インフィネオン テヒノロギーズ アーゲーInfineon TechnologiesAG

    Inventor： DITTKRIST THOMAS ,  GRAF WERNER ,  KROENKE MATTHIAS

    IPC: H01L21/304 ,  H01L21/768 ,  H01L23/522

    CPC classification number: H01L21/31053

    Abstract: PROBLEM TO BE SOLVED: To provide a simplified method for processing a structure surface so as to contain a surface higher in a first region and a surface lower in a second region.
    SOLUTION: A plurality of layers are formed on a surface, and a lower layer 13 indicates polishing rate higher than that for an upper layer 14, and also, the thicknesses of the plurality of layers are greater than a step height. Thereafter, the plurality of layers are chemically and mechanically polished so as to remove at least a part of the lower layer 13 in the first region. By the use of this method, a leveling can yet be enhanced further. Further, after a wet-cleaning process, a small upper contact opening is obtained, and deformation of the contact opening caused by an annealing processing is decreased.
    COPYRIGHT: (C)2006,JPO&NCIPI

    Abstract translation: 要解决的问题：提供一种用于处理结构表面以便包含第一区域中较高的表面和在第二区域中较低的表面的简化方法。 解决方案：在表面上形成多个层，下层13表示比上层14高的抛光速率，并且多层的厚度大于台阶高度。 此后，多层化学和机械抛光，以便去除第一区域中的下层13的至少一部分。 通过使用该方法，还可以进一步提高调平。 此外，在湿式清洁处理之后，获得小的上接触开口，并且由退火处理引起的接触开口的变形减小。 版权所有（C）2006，JPO＆NCIPI

    METHOD FOR FABRICATING A SEMICONDUCTOR PRODUCT
    2.
    发明申请
    METHOD FOR FABRICATING A SEMICONDUCTOR PRODUCT 审中-公开
    一种用于生产半导体产品

    公开(公告)号：WO03015161A3

    公开(公告)日：2003-09-25

    申请号：PCT/EP0208484

    申请日：2002-07-30

    Applicant: INFINEON TECHNOLOGIES AG ,  GRAF WERNER ,  KIESLICH ALBRECHT

    Inventor： GRAF WERNER ,  KIESLICH ALBRECHT

    IPC: H01L21/8239 ,  H01L21/8242 ,  H01L27/105

    CPC classification number: H01L27/10894 ,  H01L27/105 ,  H01L27/1052 ,  H01L27/10873

    Abstract: The invention relates to a method for integrating field-effect transistors for memory and logic applications in a semiconductor substrate (22). According to said method, the gate dielectric (2) and a semiconductor layer (4) are firstly deposited, on the whole surface thereof, both in the logic and memory areas (6) and (8). The gate electrodes (12) are first of all formed in the memory area (8) from these layers. The source and drain regions (56) are implanted and the memory area (8) is coated with an insulating material (20) in a planarized manner. Only then are the gate electrodes (21) formed in the logic area from the semiconductor layer (4) and the gate dielectric (2).

    Abstract translation: 它提出了一种用于集成Feldeffekttransi打扰的用于存储和Logikanwendungenin的半导体衬底（22）的方法，其中首先将Gatedie-lektrikum（2）和（4）中的半导体层两者的逻辑和存储器区域（6）和 （8）被沉积在整个表面上。 对于这些层，首先形成于存储区域（8），所述源和漏区（56）被注入的栅电极（12）和所述存储区域（8）用绝缘材料（20）覆盖的平坦化。 从半导体层（4）和在逻辑区域中的栅极电介质（2）上形成的栅极电极（21）随后仅。

    Production of a memory component, with a contact hole plane, uses a semiconductor substrate with prepared cell field and logic zones and surface gate electrode conductor paths
    3.
    发明专利
    Production of a memory component, with a contact hole plane, uses a semiconductor substrate with prepared cell field and logic zones and surface gate electrode conductor paths 未知

    公开(公告)号：DE102004020935B3

    公开(公告)日：2005-09-01

    申请号：DE102004020935

    申请日：2004-04-28

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： GRAF WERNER ,  KROENKE MATTHIAS

    IPC: H01L21/283 ,  H01L21/768 ,  H01L21/8242

    Abstract: To produce a contact hole plane, in a memory component, a semiconductor substrate (10) is prepared with a cell field zone (101) and a logic zone (102) together with surface gate electrode conductor paths (11,12) under a covering layer (113,123), and an oxide layer (13) is applied. A block mask (14) at the cell fields is used for anisotropic etching of the oxide layer to free the semiconductor surface and covering layer at the logic zone, and the mask is removed. A second oxide layer is applied forming a sacrifice layer over the conductor paths, and a mask layer is deposited and structured to give openings for the bit conductor contacts for the contact openings. An anisotropic etching of the sacrifice layer forms blocks over the contact openings and the mask layer is removed. Etching of the conductor paths and semiconductor surface at the blocks gives them side covers from the two oxide layers. A filling layer is between the blocks, the sacrifice layer blocks are removed at the filling layer, and the contact openings are filled with a conductive material.

    5.
    发明专利
    未知

    公开(公告)号：DE10220189A1

    公开(公告)日：2003-11-27

    申请号：DE10220189

    申请日：2002-05-06

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： GRAF WERNER ,  BEWERSDORFF-SARLETTE ULRIKE

    IPC: H01L21/28 ,  H01L29/49 ,  H01L21/336 ,  H01L29/78

    Abstract: A gate structure of a transistor is fabricated with an additional barrier formed on a metal layer of the gate structure before the deposition of a silicon oxide layer. Applying this barrier layer on the metal layer before the deposition of the silicon oxide layer prevents an oxidation of the metal during the deposition of the silicon oxide layer. A lowering of the conductivity of the metal layer or a loss of metal through sublimating metal oxide is thereby prevented. As a result, in particular the performance of the gate structure or of the transistor is improved further. In addition, disturbing coupling effects in the circuit are significantly reduced by the use of the silicon oxide cap.

    Production of an integrated semiconductor circuit used as a MOSFET comprises applying a conducting layer on a semiconductor substrate, forming a covering layer on the conducting layer, and further processing
    6.
    发明专利
    Production of an integrated semiconductor circuit used as a MOSFET comprises applying a conducting layer on a semiconductor substrate, forming a covering layer on the conducting layer, and further processing 未知

    公开(公告)号：DE10140047A1

    公开(公告)日：2003-03-13

    申请号：DE10140047

    申请日：2001-08-16

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： GRAF WERNER

    IPC: H01L21/60 ,  H01L21/8238 ,  H01L21/8242 ,  H01L21/8234

    Abstract: Production of an integrated semiconductor circuit comprises applying a first conducting layer (1) on a semiconductor substrate; forming a first covering layer on the first conducting layer so that the covering layer extends over a first flat region (I) of the substrate; applying a second conducting layer (2) on the substrate; forming a second covering layer on the second conducting layer in a second flat region (II) so that the covering layer is separated from the boundary between the first flat region and the second flat region using a boundary region having the lowest possible thickness; and etching to remove the second conducting layer and continuing etching until the first covering layer is removed from the boundary region and a trench (G) is formed between the covering layers. Preferred Features: A barrier layer (3) is deposited in the trench to prevent ion diffusion between the two flat regions. The first covering layer is removed by anisotropic etching. An embedded DRAM is produced in the first flat region.

    7.
    发明专利
    未知

    公开(公告)号：DE10140047B4

    公开(公告)日：2006-05-04

    申请号：DE10140047

    申请日：2001-08-16

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： GRAF WERNER

    IPC: H01L21/8234 ,  H01L21/60 ,  H01L21/8238 ,  H01L21/8242

    Abstract: Integrated semiconductor circuits have MOS transistors whose gate electrodes are provided with dopings in order to set the electrical potential of the channel area by changing the ionization energy (work function) of the electrons. Transistors in semiconductor circuits, which have both a memory area and a logic area, are produced either using different dopings for pMOS and NMOS transistors in the logic area (dual work function) or using common source/drain electrodes in the memory area (borderless contact), with all the transistors in the semiconductor circuit receiving the same gate doping in the latter case. A method is proposed by which a dual work function and a borderless contact can be produced at the same time. Furthermore, the method results without any additional effort in a trench between the gate layer stacks of the memory area and of the logic area, which prevents lateral ion diffusion.

    10.
    发明专利
    未知

    公开(公告)号：DE10137678A1

    公开(公告)日：2003-02-27

    申请号：DE10137678

    申请日：2001-08-01

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： GRAF WERNER ,  KIESLICH ALBRECHT

    IPC: H01L21/8239 ,  H01L21/8242 ,  H01L27/105

    Abstract: A method for the integration of field-effect transistors for memory and logic applications in a semiconductor substrate is disclosed. The gate dielectric and a semiconductor layer are deposited over the whole area both in the logic region and in the memory region. From these layers, the gate electrodes in the memory region are formed, the source and drain regions are implanted and the memory region is covered in a planarizing manner with an insulation material. Afterward, the gate electrodes are formed from the semiconductor layer and the gate dielectric in the logic region.

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