公开(公告)号：DE10334433A1

公开(公告)日：2005-03-03

申请号：DE10334433

申请日：2003-07-28

Applicant: INFINEON TECHNOLOGIES AG

Inventor： WERNER WOLFGANG ,  GRAF ALFONS ,  KLOTZ FRANK ,  SCHULZ-LINKHOLT CHRISTOPH

IPC: H01H37/76 ,  H01L23/34 ,  H01L23/485 ,  H01L23/49 ,  H01L29/78 ,  H01L23/62 ,  H01H85/11

Abstract: A device for interrupting the current flow to a semiconductor body (1) of a semiconductor component comprises a connecting unit for connecting the component to an external current cycle, and a connecting line (5) arranged between the connecting line and the semiconductor body.

公开(公告)号：DE10334433B4

公开(公告)日：2009-10-22

申请号：DE10334433

申请日：2003-07-28

Applicant: INFINEON TECHNOLOGIES AG

Inventor： WERNER WOLFGANG ,  GRAF ALFONS ,  KLOTZ FRANK ,  SCHULZ-LINKHOLT CHRISTOPH

IPC: H01L23/62 ,  H01H37/76 ,  H01H85/11 ,  H01L23/34 ,  H01L23/485 ,  H01L23/49 ,  H01L29/78

公开(公告)号：DE50210511D1

公开(公告)日：2007-08-30

申请号：DE50210511

申请日：2002-04-11

Applicant: INFINEON TECHNOLOGIES AG

Inventor： KLOTZ FRANK ,  PETZOLDT JUERGEN ,  RAFOTH AXEL

IPC: H02M1/15 ,  H02M1/14

Abstract: A voltage stabilization circuit is configured between two signal lines. Each of the signal lines carries a signal, and an interference signal is superimposed on at least one of the signals. The voltage stabilization circuit includes an amplifier circuit that provides an anti-phase signal obtained as an amplified difference between the interference signal and a reference signal. The anti-phase signal has a phase that is opposite the phase of the interference signal. The configuration further includes a matching circuit, which is connected in series with the amplifier circuit, and which generates a compensation signal from the anti-phase signal and superimposes the compensation signal on the signal that is superimposed with the interference signal.

公开(公告)号：DE59801699D1

公开(公告)日：2001-11-15

申请号：DE59801699

申请日：1998-05-05

Applicant: INFINEON TECHNOLOGIES AG

Inventor： KLOTZ FRANK ,  LORENZ LEO

IPC: H02M1/12 ,  H02M1/14 ,  H02M7/00

Abstract: A power semiconductor array on a direct copper bonding (DCB) semiconductor substrate is created, in which the interference emissions propagated via its terminal lines are eliminated, or at least greatly reduced, directly on the semiconductor device. The power semiconductor array on the DCB substrate includes a first intermediate circuit terminal connected to a positive potential, a second intermediate circuit terminal connected to a negative potential, and at least one load terminal. The power semiconductor array further includes at least two power switches for connecting the load terminal to the first and second intermediate circuit terminals in alternation. The power semiconductor array is characterized by bridging connections that connect at least some of the terminals of the power semiconductor array that lead to the outside to one another in pairs, so that interference circuits within the power semiconductor array are closed.

公开(公告)号：DE102017106027A1

公开(公告)日：2017-09-28

申请号：DE102017106027

申请日：2017-03-21

Applicant: INFINEON TECHNOLOGIES AG

Inventor： KLOTZ FRANK ,  CORDES STEPHAN

IPC: H02M1/12

Abstract: Bei manchen Beispielen ist ein Schaltkreis dazu konfiguriert, ein erstes Signal wenigstens teilweise basierend auf einem Eingangssignal zu erzeugen, wobei das erste Signal ein Gleichtaktsignal und ein Lastsignal umfasst. Der Schaltkreis ist ferner dazu konfiguriert, ein zweites Signal wenigstens teilweise basierend auf dem Eingangssignal zu erzeugen, wobei das zweite Signal eine invertierte Version des Gleichtaktsignals umfasst. Der Schaltkreis ist ferner dazu konfiguriert, das erste Signal und das zweite Signal an eine Last anzulegen.

公开(公告)号：DE10124114A1

公开(公告)日：2002-12-05

申请号：DE10124114

申请日：2001-05-17

Applicant: INFINEON TECHNOLOGIES AG

Inventor： KLOTZ FRANK ,  RAFOTH AXEL ,  PETZOLD JUERGEN

IPC: H02M1/15 ,  G05F1/10 ,  H04B15/00

Abstract: The invention relates to a circuit arrangement for voltage stabilisation, arranged between two signal lines, each with a signal, whereby an interference signal is superimposed on at least one signal, comprising an amplifier circuit, which records a signal derived from the interference signal as the difference from a reference signal, amplifies the above and generates a counter-phase signal to the above. Said arrangement further comprises a matching circuit in series with the amplifier circuit, which generates a compensation signal from the counter-phase signal and superimposes the same on the signal, superimposed with the interference potential.

公开(公告)号：DE19848829C2

公开(公告)日：2002-10-10

申请号：DE19848829

申请日：1998-10-22

Applicant: INFINEON TECHNOLOGIES AG

Inventor： BERTELE MARTIN ,  SANDER RAINALD ,  KLOTZ FRANK

IPC: H03K17/16 ,  H03K6/04 ,  H03K17/687