公开(公告)号：DE50213539D1

公开(公告)日：2009-06-25

申请号：DE50213539

申请日：2002-08-10

Applicant: INFINEON TECHNOLOGIES AG

Inventor： KOCK ERNST-JOSEF DR ,  ROHM PETER ,  TILLMANN BERTHOLD

IPC: G11C19/00 ,  G11C19/28

Abstract: The control register (SR) is formed by a shift register, whose elements (Rx) are distributed, individually or in groups, over the circuit, with the control elements, or their groups located near to controllable elements. The loading is carried out so that the data to be loaded is written in parallel into the data register, formed by a shift register, supplied sequentially to control register, and taken over by it in shift clock of the data register.

公开(公告)号：DE59914063D1

公开(公告)日：2007-02-01

申请号：DE59914063

申请日：1999-01-21

Applicant: INFINEON TECHNOLOGIES AG

Inventor： KOCK ERNST-JOSEF DR

IPC: G06F12/06 ,  G06F13/14 ,  G06F13/40 ,  G06F13/42

Abstract: The data generation method uses identification data for the peripheral units (EPx0,...EPxn) held in read/write memory elements (S0,..Sn) associated with the units. The data is combined with hardware data to provide the identification data for each peripheral unit. The data held in each memory element is generated via a programme executed by the identified peripheral unit, or it is provided by an external memory device.