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    4.
    发明专利
    未知

    公开(公告)号：DE59914398D1

    公开(公告)日：2007-08-16

    申请号：DE59914398

    申请日：1999-05-05

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： BARRENSCHEEN JENS DR ,  FRENZL GUNTHER ,  ROHM PETER

    IPC: G06F3/05 ,  H03M1/12 ,  G06F9/46 ,  H03K5/13

    Abstract: The clock generator includes request signal generation devices (7-21) for producing a first request signal (20) during a periodically repeating, predetermined first period of time (TG)for an A/D conversion of an analog signal through the A/D converter (5). The request signal generation devices are designed in such way, that they produce a second request signal (21) from a predetermined point in time (Tmax) before the end and up to the end of the predetermined first period, which is to be evaluated in combination with the first request signal for the A/D conversion.

    5.
    发明专利
    未知

    公开(公告)号：DE10146516A1

    公开(公告)日：2003-04-24

    申请号：DE10146516

    申请日：2001-09-21

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： ROHM PETER

    IPC: G06F12/14 ,  G06F21/52 ,  G06F21/71 ,  G06F21/79

    Abstract: When access to proprietary data or sensitive information stored in a memory device of a programmable unit is attempted, a check is carried out to determine whether the requested access has been or could have been initiated by someone who is not authorized to do so, and in that the memory device outputs requested data, and/or stores data which is supplied to it only when the check shows that it can be assumed that the relevant access has not been initiated or could not have been initiated by someone who is not authorized to do so. Access is controlled, for example, by identifying the source of the requested access, or by associating the requested access with the execution of a secure command.

    7.
    发明专利
    未知

    公开(公告)号：DE10142675A1

    公开(公告)日：2003-04-03

    申请号：DE10142675

    申请日：2001-08-31

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： ROHM PETER ,  TILLMANN BERTHOLD ,  KOCK ERNST JOSEF

    IPC: G11C19/00 ,  G11C19/28 ,  G05B19/07

    Abstract: The control register (SR) is formed by a shift register, whose elements (Rx) are distributed, individually or in groups, over the circuit, with the control elements, or their groups located near to controllable elements. The loading is carried out so that the data to be loaded is written in parallel into the data register, formed by a shift register, supplied sequentially to control register, and taken over by it in shift clock of the data register.

    8.
    发明专利
    未知

    公开(公告)号：DE59904178D1

    公开(公告)日：2003-03-06

    申请号：DE59904178

    申请日：1999-07-05

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： ROHM PETER ,  LETEINTURIER PATRICK

    IPC: G06F1/06 ,  G06F7/62 ,  G06F7/68

    Abstract: A method and an apparatus for generating clock signals is described, by which a period of time can be subdivided into a desired number of essentially equal-length segments. The method and the apparatus are distinguished in that the clock signals are generated based on the outcomes of a repeated subtraction of a first value from a second value. The first value depends on the number of segments into which the period of time to be subdivided is to be subdivided, and the second value depends on the duration of the period of time to be subdivided.

    9.
    发明专利
    未知

    公开(公告)号：DE50213539D1

    公开(公告)日：2009-06-25

    申请号：DE50213539

    申请日：2002-08-10

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： KOCK ERNST-JOSEF DR ,  ROHM PETER ,  TILLMANN BERTHOLD

    IPC: G11C19/00 ,  G11C19/28

    Abstract: The control register (SR) is formed by a shift register, whose elements (Rx) are distributed, individually or in groups, over the circuit, with the control elements, or their groups located near to controllable elements. The loading is carried out so that the data to be loaded is written in parallel into the data register, formed by a shift register, supplied sequentially to control register, and taken over by it in shift clock of the data register.

    10.
    发明专利
    未知

    公开(公告)号：DE50012823D1

    公开(公告)日：2006-06-29

    申请号：DE50012823

    申请日：2000-03-01

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： ROHM PETER ,  LETEINTURIER PATRICK

    IPC: H03K21/00 ,  H03K21/40

    Abstract: The arrangement is configurable by varying the position and/or size of a time window to be taken into account of during the determination and/or varying the bits of the counter state to be taken into account during the determination. An independent claim is also included for a method of determining whether a counter has reached defined count or not.

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