公开(公告)号：DE60210170T2

公开(公告)日：2006-11-02

申请号：DE60210170

申请日：2002-07-15

Applicant: INFINEON TECHNOLOGIES AG

Inventor： KUZMENKA MAKSIM ,  KOROTKOV KONSTANTIN

IPC: G06F13/40

Abstract: A memory system comprises a memory controller (14), a plurality of memory modules (10, 12) and a memory bus (16) connected to the memory controller (14) and branching into a plurality of sub-busses (20, 22), each of which is connected to a memory module (10, 12). A sub-bus (20, 22) has a diode (24, 26) associated therewith for isolating a memory module (10, 12) connected to that sub-bus (20, 22) from the memory bus (16).

公开(公告)号：DE60210170D1

公开(公告)日：2006-05-18

申请号：DE60210170

申请日：2002-07-15

Applicant: INFINEON TECHNOLOGIES AG

Inventor： KUZMENKA MAKSIM ,  KOROTKOV KONSTANTIN

IPC: G06F13/40

Abstract: A memory system comprises a memory controller (14), a plurality of memory modules (10, 12) and a memory bus (16) connected to the memory controller (14) and branching into a plurality of sub-busses (20, 22), each of which is connected to a memory module (10, 12). A sub-bus (20, 22) has a diode (24, 26) associated therewith for isolating a memory module (10, 12) connected to that sub-bus (20, 22) from the memory bus (16).

公开(公告)号：DE10218513A1

公开(公告)日：2003-11-13

申请号：DE10218513

申请日：2002-04-25

Applicant: INFINEON TECHNOLOGIES AG

Inventor： KOROTKOV KONSTANTIN

IPC: H04L25/49 ,  G06F13/38 ,  G11C7/10

Abstract: To transmit digital signals, binary signals are transformed into a series of pulses, the pulses being modulated in their pulse length as a function of an information content of the binary signals. In a corresponding circuit configuration, a modulation unit is connected to a first signal line for receiving the binary signals, the modulation unit transforming the received binary signals into the series of pulses and outputting them to a second signal line. In the process, a signal level of the pulses is also varied as a function of a state of one of the binary signals. By using a modulated pulse it is possible to transmit more than one data bit on a single data line during a clock cycle. This permits a comparatively high data throughput rate.