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公开(公告)号：WO0111787A2
公开(公告)日：2001-02-15
申请号：PCT/DE0002570
申请日：2000-08-02
Applicant: INFINEON TECHNOLOGIES AG , LAASER PETER
Inventor： LAASER PETER
IPC: H03M3/04
Abstract: The invention relates to a sigma-delta A/D converter, comprising at least one analog signal input (1, 2) for applying an analog input signal, a subtraction mechanism (3) that has multiple capacitors (20) which are used for sampling the input signal during a sampling phase and which can be switched to reference voltage sources (7, 8, 9) during an integration phase according to control signals; an integrator (10) for integrating the output signal of the subtraction mechanism (3) during the integration phase, a quantifier (13) for analog/digital conversion of the output signal of the integrator (10) for emitting a digitised output signal to a digital signal output (14); and a control logic (16) for forming the control signals in such a way as to minimise the current load of the reference voltage sources (7, 8, 9) during the integration phase.
Abstract translation: 具有Σ-ΔA / D转换器的至少一个模拟信号输入端（1,2）用于施加一个模拟输入信号，减法器（3），具有用于在一采样阶段采样输入信号的多个电容器（20），所述电容器 （20）在积分阶段到参考电压源（7，8，9）是响应于控制信号，一个积分器（10），用于所述减法元件的输出信号在积分阶段期间（3），量化器（13），用于模拟/数字积分切换 用于提供数字化输出信号为数字信号输出（14），并与用于形成控制信号，使得所述基准电压源的电流负载（7，8，9）在积分阶段期间的控制逻辑（16）最小化的积分器（10）的输出信号的转换 是。
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公开(公告)号：WO03009475A3
公开(公告)日：2003-09-18
申请号：PCT/EP0206402
申请日：2002-06-11
Applicant: INFINEON TECHNOLOGIES AG , HANNEBERG ARMIN , LAASER PETER
Inventor： HANNEBERG ARMIN , LAASER PETER
IPC: H03K19/0175 , H03K17/041 , H03K17/693 , H04L25/02
CPC classification number: H04L25/028 , H03K17/04106 , H03K17/693 , H04L25/0272
Abstract: A line driver which is especially suitable for wirebound transmission of data at high bit rates, comprising several parallel-connected driver stages (3) respectively comprising a first pair of transistors consisting of two transistors (4,5) which are controlled in a differential manner according to digital data to be transmitted, and a second pair of transistors (6,7). The transistors belonging to the second pair of transistors (6,7) are series-connected to a corresponding transistor (4,5) of the first pair of transistors. The individual driver stages (3) are connected by the transistors (6, 7) of the second pair of transistors in a parallel manner to both line terminals of the line driver. Each driver stage (3) is associated with a control circuit (2) with transfer gates (14, 15), producing the differential control signals (VGA, VGB) for the two transistors (4, 5) of the corresponding first pair of transistors.
Abstract translation: 线路驱动器，这是特别适合于以高比特率基于有线的数据传输，包括若干并联连接的驱动器级3，其在每种情况下在响应具有两个第一晶体管对以传送数字数据的差分驱动晶体管4，5和第二晶体管对6，包括7 所述第二对晶体管6的所述的晶体管，7串联连接与所述第一晶体管对相应的晶体管4,5。 各个驱动级3经由晶体管6，在平行于第二晶体管对的线路驱动器的两个线用端子7连接。 每个驱动器级3被分配给一个控制电路2与传输门14，15，其生成差分控制信号VGA，VGB为两个晶体管4，对应的第一晶体管对5。
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公开(公告)号：WO03013084A3
公开(公告)日：2003-09-25
申请号：PCT/EP0208292
申请日：2002-07-25
Applicant: INFINEON TECHNOLOGIES AG , GREGORIUS PETER , HANNEBERG ARMIN , LAASER PETER
Inventor： GREGORIUS PETER , HANNEBERG ARMIN , LAASER PETER
IPC: H04L25/02
CPC classification number: H04L25/028 , H04L25/0272 , H04L25/0292
Abstract: The invention relates to a line driver (3) for conducting data transmissions with high bit rates, particularly for conducting wire-bound data transmissions in the full-duplex method. The line driver comprises a differential pair with differential pair transistors (14, 15) for generating transmit pulses according to the data to be transmitted, whereby the transmit pulses are output to the data transmission line (8, 9), which is connected to the line driver (3), preferably via cascode transistors (16, 17) that respectively form a cascode circuit with the differential pair transistors (14, 15). In order to simulate the behavior of the differential pair, a replica differential pair is provided with replica differential pair transistors (18, 19) that generate replica pulses, which correspond to transmit pulses and which can be fed via replica cascode transistors (20, 21) to a hybrid circuit (6) for carrying out echo compensation with regard to pulses received over the data transmission line (8, 9).
Abstract translation: 甲线驱动器（3），用于以高比特率的数据传输，特别是用于在全双工模式有线数据通信，包括：差动对与差动对晶体管（14，15），用于响应于该数据产生发送脉冲将被发送，其中，所述发送脉冲，优选地 通过级联晶体管（16，17），其形成所述差分对晶体管（14，15）的每一个包括一个共源共栅电路，连接到所述线驱动器（3）的数据传输线（8,9）被输出。 用于模拟差分对，副本差动对与复制品差动对晶体管的行为（18，19）被提供，其产生超过Replikkaskodentransistoren相应的副本的脉冲（20，21）的混合电路（6）的传输脉冲，以便在数据传输线方面进行回波消除 （8,9）可以提供接收脉冲。
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公开(公告)号：AU2002317798A1
公开(公告)日：2003-03-03
申请号：AU2002317798
申请日：2002-06-11
Applicant: INFINEON TECHNOLOGIES AG
Inventor： LAASER PETER , HANNEBERG ARMIN
IPC: H03K19/0175 , H03K17/041 , H03K17/693 , H04L25/02
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公开(公告)号：DE59903041D1
公开(公告)日：2002-11-14
申请号：DE59903041
申请日：1999-07-09
Applicant: INFINEON TECHNOLOGIES AG
Inventor： LAASER PETER
Abstract: An amplifier output stage is described containing a preliminary stage, a final stage and a control device. The quiescent current that flows through transistors of the final stage is adjusted by the preliminary stage. For this, a current that is proportional to the quiescent current is generated in the control device from which control voltages are derived and controlled. The preliminary stage contains adjustable current sources for adjusting the quiescent current in a final step which are controlled by the control voltages.
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Patent Agency Ranking
公开(公告)号：DE10050337C1
公开(公告)日：2002-01-17
申请号：DE10050337
申请日：2000-10-11
Applicant: INFINEON TECHNOLOGIES AG
Inventor： LAASER PETER
Abstract: The maximum amplitude reduction method limits the signal peaks of the transmission signal to a preset maximum amplitude, selected for ensuring that the signal.noise ratio of the transmission signal is above a minimum signal/noise ratio. The amplitude limited transmission signal is subtracted from the original transmission signal to provide a difference signal, used for compensating the echo signal variation caused by the mis-match between the transceiver and the transmission channel resulting from the amplitude limitation. An Independent claim for a transceiver with an amplitude limited transmission signal is also included.
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公开(公告)号：DE10137150A1
公开(公告)日：2003-02-27
申请号：DE10137150
申请日：2001-07-30
Applicant: INFINEON TECHNOLOGIES AG
Inventor： GREGORIUS PETER , HANNEBERG ARMIN , LAASER PETER
Abstract: A line driver ( 3 ) for transmitting data with high bit rates, in particular for wire-bound data transmission in the full-duplex process, comprises a differential pair with differential pair transistors ( 14, 15 ) for generating transmission impulses as a function of the data to be transmitted, whereby the transmission impulses are preferably output via cascode transistors ( 16, 17 ), each with the differential pair transistors ( 14, 15 ) forming a cascode circuit, onto the data transmission line ( 8, 9 ) connected to the line driver ( 3 ). For reproducing the behaviour of the differential pair a replica differential pair with replica differential pair transistors ( 18, 19 ) is provided, generating replica impulses corresponding to the transmission impulses, which replica impulses can be fed via replica cascode transistors ( 20, 21 ) to a hybrid integrated circuit ( 6 ) for effecting echo compensation in relation to impulses received via the data transmission line ( 8, 9 )
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公开(公告)号：DE10030123A1
公开(公告)日：2002-01-03
申请号：DE10030123
申请日：2000-06-20
Applicant: INFINEON TECHNOLOGIES AG
Inventor： BLON THOMAS , GROEPL MARTIN , EICHLER THOMAS , LAASER PETER
Abstract: The invention relates to a circuit arrangement for the suppression of analogue echoes, in particular for application in a hybrid circuit for DSL transmission systems, comprising a replicator (8) for emulating the behaviour of the transmission line (17). The invention further relates to a circuit (3, 4) for emulating the behaviour of the transmitter (13), which comprises at least one low-pass (3, 4). Furthermore a replicator (9, 10) for emulating the behaviour of bridge taps (14) can be provided and, additionally, a replicator (19), for emulating the behaviour of the line driver (1) can also be provided.
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公开(公告)号：DE102007040867A1
公开(公告)日：2009-03-05
申请号：DE102007040867
申请日：2007-08-29
Applicant: INFINEON TECHNOLOGIES AG
Inventor： LAASER PETER
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公开(公告)号：DE102006034560A1
公开(公告)日：2008-02-07
申请号：DE102006034560
申请日：2006-07-26
Applicant: INFINEON TECHNOLOGIES AG
Inventor： LAASER PETER
IPC: H03F1/02
Abstract: An amplifier stage includes a first and a second signal path having a series connection of a first transistor of a first conduction type which forms a control input for receiving an input signal to the amplifier stage and a second transistor of a second conduction type. The amplifier stage further includes a first and second signal output which are formed by a respective connection node of the respective first and second transistors. For each of the first and the second signal path, the amplifier stage includes a third transistor of the second conduction type which is connected to the respective second transistor as current mirror, and a fourth transistor of the first conduction type which is connected to the respective first transistor as a current mirror and which is for controlling the third transistor of the other signal path, respectively. Furthermore, for each of the first and the second signal path, a current source is provided with is connected in parallel to one of the respective first, second, third, and fourth transistors.
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