中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

12 records (took 0.027 seconds)

    1.
    发明专利
    未知

    公开(公告)号：DE10340828A1

    公开(公告)日：2005-04-28

    申请号：DE10340828

    申请日：2003-09-04

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： FINTEIS THOMAS ,  RUF WOLFGANG ,  HOFFMANN KLAUS ,  FLACH BJOERN ,  SCHNELL MARTIN ,  LOGISCH ANDREAS

    IPC: G01R31/28 ,  G01R31/3177 ,  G01R31/3187 ,  G01R31/319 ,  G06F11/00 ,  G06F11/273

    Abstract: The invention provides a test arrangement for testing circuit units under test (101, 101a-101n) having a test apparatus for holding the circuit units under test (101, 101a-101n), input/output channels (DQ0-DQn) for connecting the circuit units under test (101, 101a-101n) to the test apparatus and for data interchange, and test mode output channels (103, 103a-103n) for outputting a test result signal (104, 104a-104n), where at least one diversion unit (102, 102a-102n) for connecting one of the test mode output channels (103, 103a-103n) to one of the input/output channels (DQ0-DQn) is provided in the circuit units under test (101, 101a-101n) so that the test result signal (104, 104a-104n) which is output from the circuit unit under test (101, 101a-101n) can be diverted from the circuit unit under test (101, 101a-101n) to a prescribable one of the input/output channels (DQ0-DQn).

    2.
    发明专利
    未知

    公开(公告)号：DE102004036957B3

    公开(公告)日：2006-06-14

    申请号：DE102004036957

    申请日：2004-07-30

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： LOGISCH ANDREAS

    IPC: G01R31/3183

    Abstract: Method for the generation of test signals (TS) by means of a test signal generator to a component ( 6 ) to be tested, the test signal generator generating rising and falling signal edges which are in each case assigned to successive time windows (TS 1 -TSN) with predetermined time durations (T 0 ), having the following method steps of: determining a command sequence frequency (BAF) of the component ( 6 ) to be tested; allocating instants (TS 1 U, . . . TSNU) for rising signal edges and allocating instants (TS 1 D . . . TSND) for falling signal edges for the successive time windows (TS 1 -TSN), the instants for the rising or falling signal edges (TS 1 D, . . . TSND, TS 1 U-TSNU) that are allocated to a respective time window being allocated in each case into the time range of the time window if the command sequence frequency (BAF) is lower than a limiting frequency (GF) of the test signal generator, the said limiting frequency being determined by the predetermined time duration (T 0 ), or allocating at least one instant (TS 1 U, . . . TSNU) for a rising signal edge and allocating at least one instant (TS 1 D, . . . TSND) for a falling signal edge for the successive time windows (TS 1 -TSN), at least one allocated instant (TS 1 U, . . . TSND) for a rising or falling signal edge being allocated into a time range of one of the following time windows if the command sequence frequency (BAF) is higher than the limiting frequency (GF) of the test signal generator; generating the test signal (TS) with the respective signal edges at the allocated instants (TS 1 U, . . . TSND) and applying the corresponding test signal (TS) to the component ( 6 ) to be tested.

    7.
    发明专利
    未知

    公开(公告)号：DE10324080B4

    公开(公告)日：2006-03-23

    申请号：DE10324080

    申请日：2003-05-27

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： RUF WOLFGANG ,  FLACH BJOERN ,  SCHNELL MARTIN ,  LOGISCH ANDREAS ,  SCHITTENHELM MICHAEL

    IPC: G11C29/00 ,  G01R31/317 ,  G11C29/16

    Abstract: A testing and control process for electronic chips comprises comparing command block (101) test data currents with identification units (106a-n), activating the circuits (105a-n) where the data corresponds, rough working at least one command block (102a-k) in the circuit and deactivating circuits having non-corresponding data. An independent claim is also included for a test circuit for the above process.

    8.
    发明专利
    未知

    公开(公告)号：DE10137128B4

    公开(公告)日：2005-11-17

    申请号：DE10137128

    申请日：2001-07-30

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： LOGISCH ANDREAS

    IPC: G01R1/04 ,  G01R31/28 ,  G01R31/319 ,  H01P5/08 ,  G01R31/00

    Abstract: A test apparatus comprises an input for receiving a test signal from a test signal source, wherein a signal line with a predefined characteristic wave impedance can be connected to the input. The test apparatus further comprises branching means with a first and a plurality of second terminals, the first terminal being connected to the input. The test apparatus further comprises a plurality of distribution lines, wherein each distribution line is connected to one of the plurality of second terminals of branching means, wherein one of the devices under test can be connected to each distribution line at the output side, each distribution line having a characteristic wave impedance, which is substantially equal to the product of the predefined characteristic wave impedance of the signal line and the number of distribution lines. Thus, a signal matching is given at the branching point, so that no amplitude or signal rise time distortions of the excitation signals occur at the inputs of the devices under test.

Patent Agency Ranking