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    Test circuit for testing synchronous memory circuit
    1.
    发明专利
    Test circuit for testing synchronous memory circuit 有权
    用于测试同步存储器电路的测试电路

    公开(公告)号：JP2003007086A

    公开(公告)日：2003-01-10

    申请号：JP2002098649

    申请日：2002-04-01

    Applicant: Infineon Technologies Ag ,  インフィネオン テヒノロギーズ アーゲー

    Inventor： ERNST WOLFGANG ,  KRAUSE GUNNAR ,  KUHN JUSTUS ,  LUPKE JENS ,  POECHMUELLER PETER ,  MUELLER JOCHEN ,  SCHITTENHELM MICHAEL

    IPC: G01R31/28 ,  G11C29/48 ,  G11C29/56 ,  G11C29/00

    CPC classification number: G11C29/48

    Abstract: PROBLEM TO BE SOLVED: To provide a test circuit for testing a synchronous memory circuit 3 which is operated with a high clock frequency and which is capable of adjusting test latency.
    SOLUTION: This test circuit has a frequency multiplying circuit 4 generating a high frequency clock signal for the synchronous memory chip 3 by multiplying a specific multiplication factor to the frequency of a low frequency clock from the external test unit 2, a test data generator 16 which generates test data based on a data control signal from the external test unit 2 and writes the data in the synchronous memory circuit 3, a first signal delay circuit 19 for delaying the test data by an adjustable first delay time, a second signal delay circuit 24 for delaying data from the circuit 3 to a test circuit 1 by an adjustable second delay time and a data comparing circuit 27 which compares the test data generated by the generator 16 with data from the circuit 3 and outputs a signal indicating whether the circuit 3 can operate or not to the unit 2.
    COPYRIGHT: (C)2003,JPO

    Abstract translation: 要解决的问题：提供一种用于测试以高时钟频率操作并且能够调整测试等待时间的同步存储器电路3的测试电路。 解决方案：该测试电路具有通过将特定乘法因子与来自外部测试单元2的低频时钟频率相乘的同步存储器芯片3产生高频时钟信号的倍频电路4，测试数据产生器16 基于来自外部测试单元2的数据控制信号生成测试数据，并将数据写入同步存储器电路3，第一信号延迟电路19，用于将测试数据延迟可调节的第一延迟时间;第二信号延迟电路24 用于通过可调节的第二延迟时间将电路3到测试电路1的数据延迟到数据比较电路27，数据比较电路27将由发生器16产生的测试数据与来自电路3的数据进行比较，并输出指示电路3是否可以 操作或不操作本机2。

    2.
    发明专利
    未知

    公开(公告)号：DE50112029D1

    公开(公告)日：2007-03-29

    申请号：DE50112029

    申请日：2001-06-28

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： ERNST WOLFGANG ,  KRAUSE GUNNAR ,  KUHN JUSTUS ,  LUEPKE JENS ,  MUELLER JOCHEN ,  POECHMUELLER PETER ,  SCHITTENHELM MICHAEL

    IPC: G11C29/00 ,  G01R31/3183 ,  G11C29/10

    Abstract: The method and the device generate digital signal patterns. Signal patterns or signal pattern groups are stored in a very small buffer register. The position of a following signal pattern or following signal pattern group is also stored in the form of a branch address, together with each signal pattern or each signal pattern group. A simple control logic circuit receives a control signal and determines whether the content of the currently addressed group is output continuously or the following group given by the branch address stored in the register is output after the currently selected group has been completely output. The novel method and device can advantageously be used for testing semiconductor memories and implemented in a cost-effective semiconductor circuit which is remote from a conventional test system.

    4.
    发明专利
    未知

    公开(公告)号：DE10324080B4

    公开(公告)日：2006-03-23

    申请号：DE10324080

    申请日：2003-05-27

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： RUF WOLFGANG ,  FLACH BJOERN ,  SCHNELL MARTIN ,  LOGISCH ANDREAS ,  SCHITTENHELM MICHAEL

    IPC: G11C29/00 ,  G01R31/317 ,  G11C29/16

    Abstract: A testing and control process for electronic chips comprises comparing command block (101) test data currents with identification units (106a-n), activating the circuits (105a-n) where the data corresponds, rough working at least one command block (102a-k) in the circuit and deactivating circuits having non-corresponding data. An independent claim is also included for a test circuit for the above process.

    7.
    发明专利
    未知

    公开(公告)号：DE10034899C1

    公开(公告)日：2002-07-04

    申请号：DE10034899

    申请日：2000-07-18

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： ERNST WOLFGANG ,  KRAUSE GUNNAR ,  KUHN JUSTUS ,  LUPKE JENS ,  MUELLER JOCHEN ,  POECHMUELLER PETER ,  SCHITTENHELM MICHAEL

    IPC: G11C29/56 ,  G01R31/3183 ,  G11C29/00

    Abstract: The system enables testing fast synchronous semiconductor circuits, particularly semiconductor memory chips. Various test signals such as test data, data strobe signals, control/address signals are combined to form signal groups and controllable transmit driver and receiver elements allocated to them are in each case jointly activated or, respectively, driven by timing reference signals generated by programmable DLL delay circuits. A clock signal generated in a clock generator in the BOST semiconductor circuit is picked up at a tap in the immediate vicinity of the semiconductor circuit chip to be tested and fed back to a DLL circuit in the BOST chip where it is used for eliminating delay effects in the lines leading to the DUT and back to the BOST.

    10.
    发明专利
    未知

    公开(公告)号：DE10113458C2

    公开(公告)日：2003-03-20

    申请号：DE10113458

    申请日：2001-03-19

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： POECHMUELLER PETER ,  ERNST WOLFGANG ,  KRAUSE GUNNAR ,  KUHN JUSTUS ,  LUEPKE JENS ,  MUELLER JOCHEN ,  SCHITTENHELM MICHAEL

    IPC: G11C29/48 ,  G11C29/00

    Abstract: Test circuit for testing a circuit (3) which is clocked with a high-frequency clock signal and needs to be tested, where the test circuit (1) has: (a) a frequency multiplication circuit (8) which multiplies the clock frequency of a clock signal (CLKTest), output by a tester (2), for producing the high-frequency clock signal (CLKDUT) by a frequency multiplication factor (k); (b) a control signal input bus (14) for receiving various external control signals (RAS, CAS, WE, CS) for the circuit (3) which is to be tested from the tester (2), where each control signal (RAS, CAS, WE, CS) is received in parallel via a plurality of control lines whose number is respectively equal to the frequency multiplication factor (k); (c) a parallel/serial converter (17) which is clocked with the high-frequency clock signal, is connected to the control signal input bus (14) and outputs each control signal to the circuit (3) to be tested via a control line of a control signal output bus (23, 25); and (d) a decoder circuit (19) which is clocked with the high-frequency clock signal and produces internal control signals (R/W) for the test circuit (1) on the basis of the control signals (CAS, RAS, WE, CS) which are on the control signal input bus (14), so that additional external control lines are not needed.

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