公开(公告)号：DE102004055457A1

公开(公告)日：2006-05-24

申请号：DE102004055457

申请日：2004-11-17

Applicant: INFINEON TECHNOLOGIES AG

Inventor： ZUCKERSTAETTER ANDREA ,  MERGENTHALER MAX

IPC: G06F17/50 ,  G06F11/273

Abstract: Method for checking a circuit layout for a semiconductor apparatus, including: (a) recording a circuit layout which has been created; (b) carrying out a test to determine whether predeterminable conditions are satisfied in the circuit layout; (c) if at least one predeterminable condition is not satisfied, (c1) determining position data for the at least one circuit part of the circuit layout for which at least one predeterminable condition is not satisfied; and (d) carrying out a simulation for the at least one circuit part determined in step (c), in order to obtain a simulation result.