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11 records (took 0.022 seconds)

    1.
    发明专利
    未知

    公开(公告)号：DE10154505A1

    公开(公告)日：2003-05-15

    申请号：DE10154505

    申请日：2001-11-07

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： ZUCKERSTAETTER ANDREA ,  SCHAEFER ANDRE

    IPC: G11C5/14 ,  G11C7/04

    Abstract: A memory device includes a memory module, a control unit and a bus connected to the memory module and the control unit. In an accessing operation of the memory module via bus, the control unit applies a first command which causes high power consumption in the memory module, to the memory module via part of the bus only.

    3.
    发明专利
    未知

    公开(公告)号：DE10140761B4

    公开(公告)日：2004-08-26

    申请号：DE10140761

    申请日：2001-08-20

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： ZUCKERSTAETTER ANDREA ,  SCHAEFER ANDRE

    IPC: H01L21/673 ,  H01L21/687 ,  H01L21/68

    Abstract: The present invention provides a wafer handling device having a base plate (G; G'), which has a first and a second supporting surface for a respective wafer (W1, W2) to be laid on; and a fixing device (K1, K2, S; K1', K2', S') for the detachable fixing of the respective wafer (W1, W2) on the first and second supporting surface; the fixing device (K1, K2, S; K1', K2', S') being configured in such a way that it contacts the respective wafer (W1, W2) only in the outer edge region of the side facing away from the supporting surface.

    5.
    发明专利
    未知

    公开(公告)号：DE10140761A1

    公开(公告)日：2003-03-13

    申请号：DE10140761

    申请日：2001-08-20

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： ZUCKERSTAETTER ANDREA ,  SCHAEFER ANDRE

    IPC: H01L21/673 ,  H01L21/687 ,  H01L21/68

    Abstract: The present invention provides a wafer handling device having a base plate (G; G'), which has a first and a second supporting surface for a respective wafer (W1, W2) to be laid on; and a fixing device (K1, K2, S; K1', K2', S') for the detachable fixing of the respective wafer (W1, W2) on the first and second supporting surface; the fixing device (K1, K2, S; K1', K2', S') being configured in such a way that it contacts the respective wafer (W1, W2) only in the outer edge region of the side facing away from the supporting surface.

    6.
    发明专利
    未知

    公开(公告)号：DE10154505B4

    公开(公告)日：2006-11-16

    申请号：DE10154505

    申请日：2001-11-07

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： ZUCKERSTAETTER ANDREA ,  SCHAEFER ANDRE

    IPC: G11C7/00 ,  G11C5/14 ,  G11C7/04

    Abstract: A memory device includes a memory module, a control unit and a bus connected to the memory module and the control unit. In an accessing operation of the memory module via bus, the control unit applies a first command which causes high power consumption in the memory module, to the memory module via part of the bus only.

    DRAM circuit has refresh sequence adjusting device with electrically programmable trim circuit in which frequency-determining network fuse elements are selectively changed to set state by overvoltage
    7.
    发明专利
    DRAM circuit has refresh sequence adjusting device with electrically programmable trim circuit in which frequency-determining network fuse elements are selectively changed to set state by overvoltage 未知

    公开(公告)号：DE10254076A1

    公开(公告)日：2004-02-19

    申请号：DE10254076

    申请日：2002-11-20

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： ZUCKERSTAETTER ANDREA ,  PFEIFFER JOHANN

    IPC: G11C11/406 ,  G11C11/4076 ,  G11C29/00

    Abstract: The DRAM circuit has memory cells and an access controller, a refresh device and a trim circuit for adjusting the refresh oscillator frequency to a desired value with an electrically programmable trim circuit in which fuse elements of a frequency-determining network are selectively changed from an unset state to a set state by applying an overvoltage and a fuse selection device for connecting an overvoltage source in accordance with selection. The Dynamic Random Access Memory or DRAM circuit has a number of memory cells (21) and an access controller (22), a refresh device (24) and a trim device (30,40,60,70) for adjusting the refresh oscillator (25) frequency to a desired value with an electrically programmable trim circuit (30) in which fuse elements of a frequency-determining network are selectively changed from an unset state to a set state by applying an overvoltage and a fuse selection device (70) for connecting an overvoltage source in accordance with selection data. AN Independent claim is also included for the following: (a) a method of adjusting the oscillation frequency of the refresh oscillator for a DRAM circuit.

    8.
    发明专利
    未知

    公开(公告)号：DE102004055457A1

    公开(公告)日：2006-05-24

    申请号：DE102004055457

    申请日：2004-11-17

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： ZUCKERSTAETTER ANDREA ,  MERGENTHALER MAX

    IPC: G06F17/50 ,  G06F11/273

    Abstract: Method for checking a circuit layout for a semiconductor apparatus, including: (a) recording a circuit layout which has been created; (b) carrying out a test to determine whether predeterminable conditions are satisfied in the circuit layout; (c) if at least one predeterminable condition is not satisfied, (c1) determining position data for the at least one circuit part of the circuit layout for which at least one predeterminable condition is not satisfied; and (d) carrying out a simulation for the at least one circuit part determined in step (c), in order to obtain a simulation result.

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