公开(公告)号：DE102005039394B4

公开(公告)日：2008-08-28

申请号：DE102005039394

申请日：2005-08-20

Applicant: INFINEON TECHNOLOGIES AG

Inventor： HOFSAES MARKUS ,  NASH EVA-MARIA

IPC: G06F17/50 ,  H01L21/768 ,  H01L21/822

Abstract: A layout comprises a plurality of elemental areas which define the shape and arrangement of patterns of an integrated circuit. A method for searching for potential faults in the layout begins with dividing the layout into sections. One of a number of predetermined classes is allocated to a section by means of allocation criteria. An evaluation criterion allocated to the class which was allocated to the section is then applied to the section in order to obtain an evaluation result. Each section is then identified as potentially faulted in dependence on the evaluation result.

公开(公告)号：DE102005039394A1

公开(公告)日：2007-03-01

申请号：DE102005039394

申请日：2005-08-20

Applicant: INFINEON TECHNOLOGIES AG

Inventor： HOFSAES MARKUS ,  NASH EVA-MARIA

IPC: G06F17/50 ,  H01L21/768 ,  H01L21/822

Abstract: A layout comprises a plurality of elemental areas which define the shape and arrangement of patterns of an integrated circuit. A method for searching for potential faults in the layout begins with dividing the layout into sections. One of a number of predetermined classes is allocated to a section by means of allocation criteria. An evaluation criterion allocated to the class which was allocated to the section is then applied to the section in order to obtain an evaluation result. Each section is then identified as potentially faulted in dependence on the evaluation result.