公开(公告)号：DE10241045B4

公开(公告)日：2006-07-20

申请号：DE10241045

申请日：2002-08-30

Applicant: INFINEON TECHNOLOGIES AG

Inventor： SCHMID PETER ,  PETTER ROBERT ,  DROEGE ELMAR ,  GEWALD MANFRED ,  REZNIK DANIEL ,  KAESEMODEL THOMAS

IPC: G01R31/26 ,  G01R31/28

Abstract: An electronic component (L) on wafer test procedure tests single or groups (100, 110, 120) of LED (Light Emitting Diode) or VCSEL (Vertical Cavity Self Emitting Laser) diode components after wafer processing using a monolithic integrated semiconductor wafer field effect transistor (T1, T2) switch matrix on the wafer. Includes an Independent claim for the parallel connection of protective diodes (LS).

公开(公告)号：DE10241045A1

公开(公告)日：2004-03-11

申请号：DE10241045

申请日：2002-08-30

Applicant: INFINEON TECHNOLOGIES AG

Inventor： SCHMID PETER ,  PETTER ROBERT ,  DROEGE ELMAR ,  GEWALD MANFRED ,  REZNIK DANIEL ,  KAESEMODEL THOMAS

IPC: G01R31/26 ,  G01R31/28

Abstract: An electronic component (L) on wafer test procedure tests single or groups (100, 110, 120) of LED (Light Emitting Diode) or VCSEL (Vertical Cavity Self Emitting Laser) diode components after wafer processing using a monolithic integrated semiconductor wafer field effect transistor (T1, T2) switch matrix on the wafer. Includes an Independent claim for the parallel connection of protective diodes (LS).

公开(公告)号：DE10257337A1

公开(公告)日：2003-06-26

申请号：DE10257337

申请日：2002-12-06

Applicant: INFINEON TECHNOLOGIES AG

Inventor： PETTER ROBERT ,  ZIMMERMANN ULRICH

IPC: G06F12/00 ,  G06F13/00 ,  G06F13/28 ,  G11C7/00 ,  G11C29/00

Abstract: A system and method for determining the accuracy of the states of fuses by changing, or not changing, the state of additional fuses. The system includes a memory including addressable storage elements, address fuses whereby each fuse includes a link in a connected or disconnected state and the collective state of the address fuses identifies an address value, a parity fuse whereby the fuse includes a link in a connected or disconnected state and the state of the parity fuse represents a parity value, the parity value being based on, but not equivalent to, the address of an addressable storage element, and; an output providing a value dependant upon the address value and the parity value.

公开(公告)号：DE10252318A1

公开(公告)日：2003-05-22

申请号：DE10252318

申请日：2002-11-11

Applicant: INFINEON TECHNOLOGIES AG

Inventor： PETTER ROBERT ,  VOLLRATH JOERG

IPC: H01L21/763 ,  H01L21/765 ,  H01L21/762

Abstract: A semiconductor device is provided having at least two neighboring transistors and an STI region therebetween. The STI region is provided with a voltage bias to minimize subthreshold leakage current between the neighboring transistors. A method of fabricating such a semiconductor device is also provided.