公开(公告)号：DE10034255C2

公开(公告)日：2002-05-16

申请号：DE10034255

申请日：2000-07-14

Applicant: INFINEON TECHNOLOGIES AG

Inventor： JOHNSON BRET ,  PLAETTNER ECKHARD ,  SCHNEIDER HELMUT

IPC: G11C7/06 ,  G11C7/10 ,  G11C11/4091 ,  G11C11/407

Abstract: A circuit arrangement for reading and writing binary information to a storage location array having a matrix-type arrangement of rows and columns, has a switching device (T9) which interrupts the current supply, after excitation of a any word-line, to the latch-flip-flops (T1-T4) in the write-read circuits (LV2) under control of a column-selection signal (SAS), at a time-point not before the relevant latch-flip-flop has assumed a condition indicating the information content of the accessed memory location, and which at the latest occurs in the active interval of the relevant column-selection signal.

公开(公告)号：DE10034255A1

公开(公告)日：2002-01-31

申请号：DE10034255

申请日：2000-07-14

Applicant: INFINEON TECHNOLOGIES AG

Inventor： JOHNSON BRET ,  PLAETTNER ECKHARD ,  SCHNEIDER HELMUT

IPC: G11C7/06 ,  G11C7/10 ,  G11C11/4091 ,  G11C11/407

Abstract: A circuit arrangement for reading and writing binary information to a storage location array having a matrix-type arrangement of rows and columns, has a switching device (T9) which interrupts the current supply, after excitation of a any word-line, to the latch-flip-flops (T1-T4) in the write-read circuits (LV2) under control of a column-selection signal (SAS), at a time-point not before the relevant latch-flip-flop has assumed a condition indicating the information content of the accessed memory location, and which at the latest occurs in the active interval of the relevant column-selection signal.