公开(公告)号：DE59608209D1

公开(公告)日：2001-12-20

申请号：DE59608209

申请日：1996-06-03

Applicant: INFINEON TECHNOLOGIES AG

Inventor： THEWES ROLAND ,  PRANGE STEFAN ,  WOHLRAB ERDMUTE ,  WEBER WERNER

IPC: G01R19/165 ,  G06F7/501 ,  G06F7/52 ,  G06F7/523 ,  G06F7/53 ,  G06G7/12 ,  G06G7/16 ,  H03K5/08 ,  H03K17/30

Abstract: PCT No. PCT/DE96/00971 Sec. 371 Date Dec. 4, 1997 Sec. 102(e) Date Dec. 4, 1997 PCT Filed Jun. 3, 1996 PCT Pub. No. WO96/42049 PCT Pub. Date Dec. 27, 1996The circuit arrangement has two electrical quantities in the form of a first quadrature-axis current component (I1) and of a second quadrature-axis current component (I2) that are compared to one another. The circuit arrangement has a first inverter unit (n1, p1) and a second inverter unit (n2, p2). Respectively one output (50, 52) of the two inverter units ((n1, p1, (n2, p2)) are coupled to an input of the respectively other inverter unit (52, 53). A reset unit (5) that initiates the comparison of the currents when activated is located between the two outputs of the two inverter units (n1, p2). When the reset unit (5) is deactivated, the output datum obtained in the evaluation remains stable.

公开(公告)号：DE59606804D1

公开(公告)日：2001-05-23

申请号：DE59606804

申请日：1996-06-04

Applicant: INFINEON TECHNOLOGIES AG

Inventor： PRANGE STEFAN ,  THEWES ROLAND ,  WOHLRAB ERDMUTE ,  WEBER WERNER

IPC: G06F7/53 ,  G06F7/00 ,  G06F7/50 ,  G06F7/501 ,  G06F7/506 ,  G06F7/52 ,  G06F7/527 ,  H03K19/08 ,  H03K19/20

Abstract: PCT No. PCT/DE96/00981 Sec. 371 Date Dec. 4, 1997 Sec. 102(e) Date Dec. 4, 1997 PCT Filed Jun. 4, 1996 PCT Pub. No. WO96/42048 PCT Pub. Date Dec. 27, 1996In a circuit arrangement wherein all logic elements can be represented in the form of a threshold value equation, for this purpose, transistors connected in parallel of a transistor unit are dimensioned in such a way that the cross-currents flowing through the transistors respectively represent a weighted summand of a first term of the threshold value equation. A second term of the threshold value equation is formed by a reference current representing the second term value. An evaluation unit compares an overall current, which results from the sum of cross-currents, with the reference current. The evaluation result is present at an output of the evaluation unit in the form of a stable output signal.

公开(公告)号：DE59606805D1

公开(公告)日：2001-05-23

申请号：DE59606805

申请日：1996-06-13

Applicant: INFINEON TECHNOLOGIES AG

Inventor： GEIB HERIBERT ,  PRANGE STEFAN

IPC: H04N7/46 ,  H04N7/50 ,  H04N19/423 ,  H04N19/426 ,  H04N19/577 ,  H04N19/61

Abstract: The method is for coding and for decoding a video data stream, only one picture which is required for the reconstruction of interpolated pictures being stored in completely decompressed form during the coding or during the decoding of the video data stream. That part of a second basic picture (G2) which is required in decompressed form for the construction or reconstruction of an interpolated picture is temporarily decompressed in each case. A further possibility envisages storing a first basic picture (G1) and the second basic picture (G2) in compressed form and in each case temporarily decompressing only those regions which are required for the construction or reconstruction of an interpolated picture.

公开(公告)号：DE59606519D1

公开(公告)日：2001-04-05

申请号：DE59606519

申请日：1996-06-03

Applicant: INFINEON TECHNOLOGIES AG

Inventor： THEWES ROLAND ,  PRANGE STEFAN ,  WOHLRAB ERDMUTE ,  WEBER WERNER

IPC: G06F7/53 ,  G06F7/501 ,  G06F7/52 ,  G06F7/523 ,  H03K5/24 ,  H03K19/20

Abstract: PCT No. PCT/DE96/00972 Sec. 371 Date Dec. 4, 1997 Sec. 102(e) Date Dec. 4, 1997 PCT Filed Jun. 3, 1996 PCT Pub. No. WO96/42050 PCT Pub. Date Dec. 27, 1996The circuit arrangement compares a quantity supplied by a first neuron MOS field effect transistor (M1) to a reference quantity that is made available by a reference source (R). A current mirror (SP) is provided therefor, this enabling a comparison of a second current (I2) supplied by a reference transistor (R) to a first current (I1) supplied by the first neuron MOS field effect transistor (M1). The evaluator circuit is activated or, respectively, decoupled by a first switch unit (S1) and a second switch unit (S2). What is thereby achieved is that no current flows in the evaluator circuit in the quiescent condition. The comparison result is applied to an inverter unit (IS). Since the inverter unit (IS) is decoupled from the evaluator circuit by the first switch unit (S1), an undefined level is never adjacent at the output (AIS) of the inverter unit (IS). This can be advantageously utilized in the further data processing in following stages.