公开(公告)号：WO02069284A8

公开(公告)日：2002-11-14

申请号：PCT/EP0201013

申请日：2002-01-31

Applicant: INFINEON TECHNOLOGIES AG ,  PALM HERBERT ,  WOHLRAB ERDMUTE ,  TADDIKEN HANS

Inventor： PALM HERBERT ,  WOHLRAB ERDMUTE ,  TADDIKEN HANS

IPC: G04F10/10 ,  G04F1/00 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/423 ,  H01L29/51 ,  H01L29/788 ,  H01L29/792

CPC classification number: H01L29/511 ,  G04F1/005 ,  G04F10/10 ,  H01L29/42324 ,  H01L29/7881 ,  H01L29/792

Abstract: The invention relates to a time-detection device using a floating-gate-cell, wherein an ON-layer structure or a ONO-layer structure is provided between the floating-gate and the control-gate. A charge injection device is supplied in order to insert the floating-gate-electrode into the nitride layer of the ON-structure or the ONO-layer structure, wherein a voltage or a voltage pulse is applied to the control-gate-electrode, the centre of gravity of the charges injected into the nitride layer being located on the defining surface. Said time-detection device also comprises a device for detecting time elapsed since injection of the charges, based on changes in the transmission behaviour of the channel area, which are effected by displacement of the centre of gravity of the charges in the nitride layer away from the defining surface.

Abstract translation: 甲时间检测装置使用在其上设置的导通层结构或浮置栅极和控制栅极之间的ONO层结构的浮动栅极单元。 电荷注入装置被提供到电荷注入到浮置栅电极并进入ON-结构或通过施加电压或电压脉冲的ONO层结构的氮化物层被施加到控制栅电极，在重力的其中一个中心 在位于所述层序列的氧化物层和氮化物层之间的界面处的氮化物层中的注入的电荷。 时间检测装置还包括用于检测由于电荷经过基于在所引起的移位远离在从接口的氮化物层的电荷的重心的沟道区域的传输行为的变化时的喷射的装置。

公开(公告)号：AU2002233313A1

公开(公告)日：2002-09-12

申请号：AU2002233313

申请日：2002-01-31

Applicant: INFINEON TECHNOLOGIES AG

Inventor： PALM HERBERT ,  WOHLRAB ERDMUTE ,  TADDIKEN HANS

IPC: G04F10/10 ,  G04F1/00 ,  G07F1/00 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/423 ,  H01L29/51 ,  H01L29/788 ,  H01L29/792

Abstract: A time recording device employs a floating gate cell, wherein an ON layer structure or an ONO layer structure is provided between floating gate and control gate. A charge injection unit is provided to inject charges into the floating gate electrode and into the nitride layer of the ON structure or the ONO structure by applying a voltage or voltage pulses to the control gate electrode, a center of concentration of the charges injected into the nitride layer being located at the interface between oxide layer and nitride layer of the layer sequence. The time recording device also includes a unit for recording a time which has elapsed since charge injection on the basis of changes in the transmission behavior of the channel region caused by a shift in the center of concentration of the charges in the nitride layer away from the interface.

公开(公告)号：DE59608209D1

公开(公告)日：2001-12-20

申请号：DE59608209

申请日：1996-06-03

Applicant: INFINEON TECHNOLOGIES AG

Inventor： THEWES ROLAND ,  PRANGE STEFAN ,  WOHLRAB ERDMUTE ,  WEBER WERNER

IPC: G01R19/165 ,  G06F7/501 ,  G06F7/52 ,  G06F7/523 ,  G06F7/53 ,  G06G7/12 ,  G06G7/16 ,  H03K5/08 ,  H03K17/30

Abstract: PCT No. PCT/DE96/00971 Sec. 371 Date Dec. 4, 1997 Sec. 102(e) Date Dec. 4, 1997 PCT Filed Jun. 3, 1996 PCT Pub. No. WO96/42049 PCT Pub. Date Dec. 27, 1996The circuit arrangement has two electrical quantities in the form of a first quadrature-axis current component (I1) and of a second quadrature-axis current component (I2) that are compared to one another. The circuit arrangement has a first inverter unit (n1, p1) and a second inverter unit (n2, p2). Respectively one output (50, 52) of the two inverter units ((n1, p1, (n2, p2)) are coupled to an input of the respectively other inverter unit (52, 53). A reset unit (5) that initiates the comparison of the currents when activated is located between the two outputs of the two inverter units (n1, p2). When the reset unit (5) is deactivated, the output datum obtained in the evaluation remains stable.

公开(公告)号：DE50202374D1

公开(公告)日：2005-04-07

申请号：DE50202374

申请日：2002-01-31

Applicant: INFINEON TECHNOLOGIES AG

Inventor： PALM HERBERT ,  WOHLRAB ERDMUTE ,  TADDIKEN HANS

IPC: G04F10/10 ,  G04F1/00 ,  G07F1/00 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/423 ,  H01L29/51 ,  H01L29/788 ,  H01L29/792

Abstract: A time recording device employs a floating gate cell, wherein an ON layer structure or an ONO layer structure is provided between floating gate and control gate. A charge injection unit is provided to inject charges into the floating gate electrode and into the nitride layer of the ON structure or the ONO structure by applying a voltage or voltage pulses to the control gate electrode, a center of concentration of the charges injected into the nitride layer being located at the interface between oxide layer and nitride layer of the layer sequence. The time recording device also includes a unit for recording a time which has elapsed since charge injection on the basis of changes in the transmission behavior of the channel region caused by a shift in the center of concentration of the charges in the nitride layer away from the interface.

公开(公告)号：DE10060652C1

公开(公告)日：2002-06-20

申请号：DE10060652

申请日：2000-12-06

Applicant: INFINEON TECHNOLOGIES AG

Inventor： WOHLRAB ERDMUTE ,  TADDIKEN HANS

IPC: H01L23/58 ,  H01L27/02 ,  H01L27/115 ,  H01L27/088

Abstract: The circuit acts as a loading detector (20), coupled via an electrical conductor (1) to the protected electronic component or electronic circuit and adopting a detectable permanent condition when the loading exceeds a given value. A control circuit is coupled to the electrical conductor via a pair of switch elements (2,3), e.g. a pair of complementary FET's connected in series, for detecting the condition of the loading detector.

公开(公告)号：DE59810754D1

公开(公告)日：2004-03-18

申请号：DE59810754

申请日：1998-12-17

Applicant: INFINEON TECHNOLOGIES AG

Inventor： WEBER WERNER DR ,  WOHLRAB ERDMUTE

IPC: G11C16/02 ,  G11C16/06 ,  G11C16/10 ,  G11C16/26

Abstract: The EPROM has a device (M1,M2,M3) for evaluating and regulating the voltage (V) of the bit line (BL). A memory cell (Z) is provided. This has a transistor with a floating gate. The control gate is connected to the word line (WL). The drain terminal is connected to the bit line and the source terminal is connected to the reference potential (GND). The bit line can be connected via a p-channel first MOS transistor (M1) to a bit line supply voltage (VBL). The gate (CH) of the first transistor (M1) can be connected via a p-channel second MOS transistor (M2) with the bit line supply voltage (VBL) and via an n-channel third MOS transistor (M3) to the reference potential. The bit line is connected to the gate of the second p-channel MOS transistor. The gate of the third transistor is connected to the input for a pulse type voltage (PHI). The method for programming the EPROM involves using the pulsed voltage and the third and first transistors to cause the bit line to be connected to the bit-line supply voltage. A pulse train with negative and positive pulses is then applied to the word line. During the negative pulse, the memory cells are programmed. During the positive pulse, it is checked whether a desired threshold voltage of the transistor of that cell has been reached. If so, the memory cell is conductive and the voltage at the bit line is reduced. The p-channel MOS transistor is closed. The bit line is then decoupled from the supply voltage and the cell is discharged to the reference potential.

公开(公告)号：DE10108913A1

公开(公告)日：2002-09-12

申请号：DE10108913

申请日：2001-02-23

Applicant: INFINEON TECHNOLOGIES AG

Inventor： TADDIKEN HANS ,  WOHLRAB ERDMUTE ,  PALM HERBERT

IPC: G04F10/10 ,  G04F1/00 ,  G07F1/00 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/423 ,  H01L29/51 ,  H01L29/788 ,  H01L29/792 ,  G04F10/00

Abstract: The invention relates to a time-detection device using a floating-gate-cell, wherein an ON-layer structure or a ONO-layer structure is provided between the floating-gate and the control-gate. A charge injection device is supplied in order to insert the floating-gate-electrode into the nitride layer of the ON-structure or the ONO-layer structure, wherein a voltage or a voltage pulse is applied to the control-gate-electrode, the centre of gravity of the charges injected into the nitride layer being located on the defining surface. Said time-detection device also comprises a device for detecting time elapsed since injection of the charges, based on changes in the transmission behaviour of the channel area, which are effected by displacement of the centre of gravity of the charges in the nitride layer away from the defining surface.

公开(公告)号：DE59606804D1

公开(公告)日：2001-05-23

申请号：DE59606804

申请日：1996-06-04

Applicant: INFINEON TECHNOLOGIES AG

Inventor： PRANGE STEFAN ,  THEWES ROLAND ,  WOHLRAB ERDMUTE ,  WEBER WERNER

IPC: G06F7/53 ,  G06F7/00 ,  G06F7/50 ,  G06F7/501 ,  G06F7/506 ,  G06F7/52 ,  G06F7/527 ,  H03K19/08 ,  H03K19/20

Abstract: PCT No. PCT/DE96/00981 Sec. 371 Date Dec. 4, 1997 Sec. 102(e) Date Dec. 4, 1997 PCT Filed Jun. 4, 1996 PCT Pub. No. WO96/42048 PCT Pub. Date Dec. 27, 1996In a circuit arrangement wherein all logic elements can be represented in the form of a threshold value equation, for this purpose, transistors connected in parallel of a transistor unit are dimensioned in such a way that the cross-currents flowing through the transistors respectively represent a weighted summand of a first term of the threshold value equation. A second term of the threshold value equation is formed by a reference current representing the second term value. An evaluation unit compares an overall current, which results from the sum of cross-currents, with the reference current. The evaluation result is present at an output of the evaluation unit in the form of a stable output signal.

公开(公告)号：DE59606519D1

公开(公告)日：2001-04-05

申请号：DE59606519

申请日：1996-06-03

Applicant: INFINEON TECHNOLOGIES AG

Inventor： THEWES ROLAND ,  PRANGE STEFAN ,  WOHLRAB ERDMUTE ,  WEBER WERNER

IPC: G06F7/53 ,  G06F7/501 ,  G06F7/52 ,  G06F7/523 ,  H03K5/24 ,  H03K19/20

Abstract: PCT No. PCT/DE96/00972 Sec. 371 Date Dec. 4, 1997 Sec. 102(e) Date Dec. 4, 1997 PCT Filed Jun. 3, 1996 PCT Pub. No. WO96/42050 PCT Pub. Date Dec. 27, 1996The circuit arrangement compares a quantity supplied by a first neuron MOS field effect transistor (M1) to a reference quantity that is made available by a reference source (R). A current mirror (SP) is provided therefor, this enabling a comparison of a second current (I2) supplied by a reference transistor (R) to a first current (I1) supplied by the first neuron MOS field effect transistor (M1). The evaluator circuit is activated or, respectively, decoupled by a first switch unit (S1) and a second switch unit (S2). What is thereby achieved is that no current flows in the evaluator circuit in the quiescent condition. The comparison result is applied to an inverter unit (IS). Since the inverter unit (IS) is decoupled from the evaluator circuit by the first switch unit (S1), an undefined level is never adjacent at the output (AIS) of the inverter unit (IS). This can be advantageously utilized in the further data processing in following stages.

公开(公告)号：DE59702679D1

公开(公告)日：2001-01-04

申请号：DE59702679

申请日：1997-07-04

Applicant: INFINEON TECHNOLOGIES AG

Inventor： THEWES ROLAND ,  WEBER WERNER ,  LUCK ANDREAS ,  WOHLRAB ERDMUTE ,  SCHMITT-LANDSIEDEL DORIS

IPC: G06G7/60 ,  H03F1/22 ,  H03F3/16 ,  H03G1/00

Abstract: Amplifier circuits having at least one neuron MOS transistor in which a coupling gate is connected to an amplifier output and at least one further coupling gate is connected with a respective amplifier input are provided. The amplifier circuit exhibits a linear transmission behavior even in large-signal operation and can be constructed using relatively few components. Furthermore, the gain is easy to set.