公开(公告)号：JP2001237285A

公开(公告)日：2001-08-31

申请号：JP2000385881

申请日：2000-12-19

Applicant: INFINEON TECHNOLOGIES AG

Inventor： ROBERT FOIRURE ,  SAVIGNAC DOMINIQUE

IPC: G01R31/28 ,  G01R31/3185 ,  G11C11/401 ,  G11C29/56 ,  H01L21/66 ,  G11C29/00

Abstract: PROBLEM TO BE SOLVED: To determine if semiconductor chips satisfy requirements or not by providing a device for testing a large number of the semiconductor chips to inspect a variety of timing parameters of the semiconductor chips on a wafer surface. SOLUTION: The device for testing a number of the semiconductor chips is configured with the following characteristics. Each of the semiconductor chips on the semiconductor wafer has at least one option pad. A test program is supplied to the semiconductor chips via the pads on the wafer surface. Thus, the semiconductor chips not satisfying the predetermined requirements for the critical parameters are removed.

公开(公告)号：JP2001102536A

公开(公告)日：2001-04-13

申请号：JP2000291017

申请日：2000-09-25

Applicant: INFINEON TECHNOLOGIES AG

Inventor： ROBERT FOIRURE

IPC: H01L27/04 ,  G01R31/3185 ,  G11C5/06 ,  G11C5/14 ,  H01L21/822

Abstract: PROBLEM TO BE SOLVED: To provide an apparatus that can reduce the number of pads for measurement in a semiconductor chip having an integrated circuit, and further to accurately cut fuses, while making the number of usable pads few. SOLUTION: An analog-to-digital converter 3 is installed. The analog-to-digital converter 3 supplies inner voltages, that are generated from various parts of an integrated circuit formed in a semiconductor chip 1 to a fuse cutter 5 via a pad 9. The fuse cutter 5 cuts fuses 7 to change the measured inner voltages to respective target voltage values.

公开(公告)号：JP2002175690A

公开(公告)日：2002-06-21

申请号：JP2001279684

申请日：2001-09-14

Applicant: INFINEON TECHNOLOGIES AG

Inventor： ROBERT FOIRURE ,  SAVIGNAC DOMINIQUE

IPC: G11C11/401 ,  G11C11/34 ,  G11C11/407 ,  H01L21/334 ,  H01L21/8242 ,  H01L27/108

Abstract: PROBLEM TO BE SOLVED: To provide an integrated memory which has memory cells and buffer capacitors in plane state arrangement being sufficiently uniform and in which comparatively high voltage tolerance can be made continuously by these buffer capacitors. SOLUTION: In this memory, each memory cell has a selective transistor and a memory capacitor, the memory capacitor is connected to one of a plurality of column lines through the selective transistor for each memory cell, a control terminal of the selective transistor is connected to one of row lines for each memory cell, each buffer capacitor is connected to another column line by a contact, and the buffer capacitor is provided so that a connection path between each buffer capacitor and contact is arranged in parallel to another row line.

公开(公告)号：JP2001111407A

公开(公告)日：2001-04-20

申请号：JP2000278531

申请日：2000-09-13

Applicant: INFINEON TECHNOLOGIES AG

Inventor： ROBERT FOIRURE

IPC: H03K19/0175 ,  G11C11/4093 ,  H03K3/3565 ,  H03K19/00

Abstract: PROBLEM TO BE SOLVED: To suppress the whole current consumption of an input buffer as much as possible while considerably reducing the required area of the input buffer during the execution of one operation mode in a semiconductor circuit provided with plural input buffers. SOLUTION: A semiconductor integrated circuit provided with 1st and 2nd modes has plural input buffers. At least one input buffer is used for controlling the switching of each of operation modes. The input buffer IB1 for controlling the switching of each of the operation modes has a driver circuit provided with an inverter circuit 11 whose static loss current is slight. Each of remaining input buffers IB1 to IBn has a differential amplifier circuit DA, which is interrupted in the 2nd mode. The minimum current consumption of the semiconductor circuit can be suppressed by the inverter circuit 11 capable of switching the modes at high reliability even with low voltage supply.