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    Integrated circuit device and method of manufacturing the same
    1.
    发明专利
    Integrated circuit device and method of manufacturing the same 有权
    集成电路装置及其制造方法

    公开(公告)号：JP2007329489A

    公开(公告)日：2007-12-20

    申请号：JP2007176125

    申请日：2007-07-04

    Applicant: Infineon Technologies Ag ,  インフィニオン テクノロジーズ アクチエンゲゼルシャフトInfineon Technologies Ag

    Inventor： ROESNER WOLFGANG ,  HOFMANN FRANZ ,  BERTAGNOLLI EMMERICH ,  GOEBEL BERND

    IPC: H01L21/8234 ,  H01L29/78 ,  H01L21/336 ,  H01L21/8239 ,  H01L21/8242 ,  H01L21/8246 ,  H01L27/04 ,  H01L27/088 ,  H01L27/105 ,  H01L27/108 ,  H01L27/112

    CPC classification number: H01L27/10876 ,  H01L27/1052 ,  H01L27/10823 ,  H01L27/112 ,  H01L27/11273

    Abstract: PROBLEM TO BE SOLVED: To provide a high-density integrated circuit device by which a floating body effect of a transistor can be avoided.
    SOLUTION: A vertical MOS transistor includes a series of layers SF, SF* arranged on a first conductive type substrate 1. The series of layers comprise a lower layer U for a first source/drain region, an intermediate layer M doped with a first conductive type to act as a channel region, and an upper layer O for a second source/drain region. A connection structure V doped with the first conductive type is arranged on a first surface of the series of layers SF, SF* to electrically connect the channel region to the substrate 1. A gate electrode of the transistor is arranged on a second surface of the series of layers SF, SF*. The connection structure V can be arranged between the series of layers SF, SF* and the same or another series of layers SF, SF*. The dimension of the connection structure V or the like can be a lithography dimension or less. The manufactured circuit is suitable for a storage cell arrangement.
    COPYRIGHT: (C)2008,JPO&INPIT

    Abstract translation: 要解决的问题：提供可以避免晶体管的浮体效应的高密度集成电路器件。 解决方案：垂直MOS晶体管包括布置在第一导电型衬底1上的一系列层SF，SF *。一系列层包括用于第一源/漏区的下层U，掺杂有 用作沟道区的第一导电类型和用于第二源极/漏极区的上层O。 掺杂有第一导电类型的连接结构V布置在一系列层SF，SF *的第一表面上，以将沟道区域电连接到衬底1.晶体管的栅极布置在第二表面上 系列SF，SF *。 连接结构V可以布置在一系列层SF，SF *和相同或另一系列层SF，SF *之间。 连接结构V等的尺寸可以是光刻尺寸或更小。 制造的电路适用于存储单元布置。 版权所有（C）2008，JPO＆INPIT

    Planar double-gate transistor and manufacturing method thereof
    2.
    发明专利
    Planar double-gate transistor and manufacturing method thereof 审中-公开
    平面双栅晶体管及其制造方法

    公开(公告)号：JP2006024951A

    公开(公告)日：2006-01-26

    申请号：JP2005200964

    申请日：2005-07-08

    Applicant: Infineon Technologies Ag ,  インフィネオン テクノロジーズ アクチエンゲゼルシャフト

    Inventor： ILICALI GUERKAN ,  LUYKEN RICHARD JOHANNES ,  ROESNER WOLFGANG

    IPC: H01L29/786 ,  H01L21/02 ,  H01L21/336 ,  H01L27/12

    CPC classification number: H01L29/66772 ,  H01L29/66628 ,  H01L29/78618 ,  H01L29/78648

    Abstract: PROBLEM TO BE SOLVED: To provide a planar self-alignment double-gate transistor by a known, simple, cost-effective manufacturing method. SOLUTION: The manufacturing method includes a step for prescribing an active region on an SOI substrate; a step for forming a first gate region 206 on the SOI substrate; a step for forming a source/drain region made of silicon germanium in the active region; a step for forming a channel region 203 from a silicon layer on the SOI substrate; a step for forming a layer 311 having a plane on the SOI substrate, the source/drain region, and the first gate region 206; a step for connecting a wafer in which a silicon oxide 413 is formed on the plane; and a step for forming a second gate region 517 facing the first gate region 206. COPYRIGHT: (C)2006,JPO&NCIPI

    Abstract translation: 要解决的问题：通过已知的，简单的，成本有效的制造方法来提供平面自对准双栅极晶体管。 解决方案：制造方法包括在SOI衬底上规定有源区的步骤; 在SOI衬底上形成第一栅极区域206的步骤; 用于在有源区中形成由硅锗制成的源/漏区的步骤; 从SOI衬底上的硅层形成沟道区203的步骤; 用于在SOI衬底，源极/漏极区域和第一栅极区域206上形成具有平面的层311的步骤; 连接在该平面上形成有氧化硅413的晶片的工序; 以及形成面对第一栅极区域206的第二栅极区域517的步骤。版权所有（C）2006，JPO＆NCIPI

    Layer structure used as double-gate field effect transistor and manufacturing method thereof
    3.
    发明专利
    Layer structure used as double-gate field effect transistor and manufacturing method thereof 审中-公开
    层状结构用作双栅场效应晶体管及其制造方法

    公开(公告)号：JP2006024950A

    公开(公告)日：2006-01-26

    申请号：JP2005200961

    申请日：2005-07-08

    Applicant: Infineon Technologies Ag ,  インフィネオン テクノロジーズ アクチエンゲゼルシャフト

    Inventor： ILICALI GUERKAN ,  LUYKEN RICHARD JOHANNES ,  ROESNER WOLFGANG

    IPC: H01L29/786

    CPC classification number: H01L29/6656 ,  H01L29/66484 ,  H01L29/7831

    Abstract: PROBLEM TO BE SOLVED: To provide a layer structure used as a double-gate field effect transistor, and to provide a method for manufacturing the layer structure.
    SOLUTION: A porous silicon layer is formed on an auxiliary substrate as a sacrifice layer. A first semiconductor layer and a first electric insulating layer are successively formed on the sacrifice layer. On the first electric insulating layer, a conductive layer is formed for laterally forming a pattern. The laterally pattern-formed conductive layer is used as a common mask for laterally pattern-forming the first electric insulating layer, the sacrifice layer, and the first semiconductor layer. A semiconductor section is formed adjacent to the sidewall of the pattern-formed sacrifice layer and that of the first pattern-formed semiconductor layer. A substrate is fixed to the upper portion of the pattern-formed conductive layer, and the material of the auxiliary substrate is removed, thus exposing the sacrifice layer. The sacrifice layer is selectively removed, thus forming a trench. In the trench, a second electric insulating layer is formed, and a conductive section is formed on the second electric insulating layer.
    COPYRIGHT: (C)2006,JPO&NCIPI

    Abstract translation: 要解决的问题：提供用作双栅极场效应晶体管的层结构，并提供一种用于制造层结构的方法。 解决方案：在辅助衬底上形成多孔硅层作为牺牲层。 在牺牲层上依次形成第一半导体层和第一电绝缘层。 在第一电绝缘层上形成用于横向形成图案的导电层。 横向图案形成的导电层用作用于横向图案形成第一电绝缘层，牺牲层和第一半导体层的通用掩模。 在图案形成的牺牲层和第一图案形成的半导体层的侧壁附近形成半导体部分。 将基板固定到图案形成的导电层的上部，并且去除辅助基板的材料，从而暴露牺牲层。 选择性地去除牺牲层，从而形成沟槽。 在沟槽中，形成第二电绝缘层，在第二电绝缘层上形成导电部。 版权所有（C）2006，JPO＆NCIPI

    Layer arrangement and manufacturing method of layer arrangement
    4.
    发明专利
    Layer arrangement and manufacturing method of layer arrangement 审中-公开
    层布置的层布置和制造方法

    公开(公告)号：JP2006024940A

    公开(公告)日：2006-01-26

    申请号：JP2005198169

    申请日：2005-07-06

    Applicant: Infineon Technologies Ag ,  インフィネオン テクノロジーズ アクチエンゲゼルシャフト

    Inventor： ILICALI GUERKAN ,  LANDGRAF ERHARD ,  ROESNER WOLFGANG ,  HOFFMANN FRANZ

    IPC: H01L29/786 ,  H01L21/02 ,  H01L21/336 ,  H01L27/12

    CPC classification number: H01L29/66772 ,  H01L29/66628 ,  H01L29/78648 ,  H01L29/78654

    Abstract: PROBLEM TO BE SOLVED: To provide a manufacturing method of a layer arrangement capable of overcoming a problem related to epitaxial growth.
    SOLUTION: In a manufacturing method of a layer arrangement of the present invention, a first layer (203) having a thickness larger than a minimum thickness for the epitaxial growth of a second layer (408) is formed, a second layer (408) is epitaxially grown on the first layer (203), and a third layer (409) is formed on the second layer (408). Further, a handling wafer (510) is joined on the third layer, and the substrate is removed from a second surface facing a first surface, and the first layer (203) is partially made to be thin from the second surface, and as a result, after making the layer thin, the first layer (203) has a thickness smaller than the minimum thickness for the epitaxial growth.
    COPYRIGHT: (C)2006,JPO&NCIPI

    Abstract translation: 要解决的问题：提供能够克服与外延生长相关的问题的层布置的制造方法。 解决方案：在本发明的层布置的制造方法中，形成厚度大于第二层（408）的外延生长的最小厚度的第一层（203），第二层（ 408）在第一层（203）上外延生长，第三层（409）形成在第二层（408）上。 此外，处理晶片（510）接合在第三层上，并且从与第一表面相对的第二表面移除基板，并且第一层（203）部分地从第二表面变薄，并且作为 结果，在使薄层变薄之后，第一层（203）的厚度小于用于外延生长的最小厚度。 版权所有（C）2006，JPO＆NCIPI

    TRANSISTOR AND INTEGRATED CIRCUIT
    6.
    发明申请
    TRANSISTOR AND INTEGRATED CIRCUIT 审中-公开
    晶体管与集成电路

    公开(公告)号：WO02091472A3

    公开(公告)日：2003-02-20

    申请号：PCT/DE0201561

    申请日：2002-04-29

    Applicant: INFINEON TECHNOLOGIES AG ,  HOFMANN FRANZ ,  ROESNER WOLFGANG

    Inventor： HOFMANN FRANZ ,  ROESNER WOLFGANG

    IPC: H01L21/8242 ,  H01L29/06 ,  H01L27/108

    CPC classification number: H01L27/10888 ,  H01L27/10855 ,  H01L27/10873 ,  H01L29/0653

    Abstract: The invention relates to a MOS transistor in which the source capacity and drain capacity are reduced relatively to the substrate, owing to the fact that an isolating element (507) made of a material with a low dielectric constant is placed under the source and drain supply. The invention also relates to an integrated circuit in which the bitline supply line capacity is reduced relatively to the substrate, owing to the fact that an isolating element (307) made of a material with a low dielectric constant is placed under the bitline supply line.

    Abstract translation: 本发明提供一种MOS晶体管，其源极和漏极电容相对于特征在于，所述源下的衬底降低和漏极每由具有低介电常数的材料构成的绝缘体元件（507）供给。 本发明还提供一种集成电路，其特征在于，相对于所述基板的位线引出配线电容由以下事实减少，根据位线引线，由具有低介电常数的材料构成的绝缘体元件（307）。

    MOLECULAR ELECTRONICS ARRANGEMENT AND METHOD FOR PRODUCING A MOLECULAR ELECTRONICS ARRANGEMENT
    9.
    发明申请
    MOLECULAR ELECTRONICS ARRANGEMENT AND METHOD FOR PRODUCING A MOLECULAR ELECTRONICS ARRANGEMENT 审中-公开
    分子电子装置和生产分子电子装置的方法

    公开(公告)号：WO03005369A3

    公开(公告)日：2003-04-17

    申请号：PCT/DE0202379

    申请日：2002-07-01

    Applicant: INFINEON TECHNOLOGIES AG ,  HARTWICH JESSICA ,  KRETZ JOHANNES ,  LUYKEN RICHARD JOHANNES ,  ROESNER WOLFGANG

    Inventor： HARTWICH JESSICA ,  KRETZ JOHANNES ,  LUYKEN RICHARD JOHANNES ,  ROESNER WOLFGANG

    IPC: B82B1/00 ,  G11C11/21 ,  G11C13/02 ,  H01L51/00 ,  H01L51/30 ,  H01L51/40 ,  H01L51/20

    CPC classification number: G11C13/0019 ,  B82Y10/00 ,  G11C13/0014 ,  H01L51/0048 ,  H01L51/005 ,  H01L51/0052 ,  H01L51/0093 ,  H01L51/0595

    Abstract: The invention relates to a molecular electronics arrangement comprising a substrate, at least one first strip conductor having a surface and being arranged in or on the substrate, a spacer which is arranged on the surface of the at least one first strip conductor and which partially covers the surface of the at least one first strip conductor, and at least one second strip conductor which is arranged on the spacer and comprises a surface which faces the surface of the at least one first strip conductor in a plane manner. The spacer partially covers the surface of the at least one second strip conductor, and defines a pre-determined distance between the at least one first strip conductor and the at least one second strip conductor. The inventive molecular electronics arrangement also comprises molecular electronics molecules which are arranged between a free region of the surface of the at least one first strip conductor and a free region of the surface of the at least one second strip conductor, the length of said molecules being essentially equal to the distance between the at least one first strip conductor and the at least one second strip conductor. The invention also relates to a method for producing a molecular electronics arrangement.

    Abstract translation: 本发明涉及一种分子电子装置的至少一个第一互连配置间隔物的表面上具有基片，至少一个第一互连，其具有表面和被布置在衬底中或上，一个其中至少一个的表面上 第一导体部分覆盖，设置在间隔件第二互连，其具有表面，该表面至少相对的第一配线面的表面，其中所述间隔，所述至少一个第二互连的表面部分地覆盖至少一个，并且其中，由所述间隔件的装置的预定 所述至少一个第一互连和所述至少限定一个第二导体轨道之间的距离，以及之间的至少一个第一互连件的表面的暴露部分和所述至少一个第二表面的未覆盖区域 导体排列的分子电子分子，其长度基本上等于至少一个第一导体迹线和至少一个第二导体迹线之间的距离。 此外，提供了用于制造分子电子器件的方法。

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