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    2.
    发明专利
    未知

    公开(公告)号：DE102004058411B3

    公开(公告)日：2006-08-17

    申请号：DE102004058411

    申请日：2004-12-03

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： ROSKOPF VALENTIN ,  WINTER RAMONA ,  SUKMAN-PRAEHOFER SIBINA ,  LACHENMANN SUSANNE

    IPC: H01L23/544 ,  H01L21/66 ,  H01L23/522

    Abstract: The invention proposes a semiconductor wafer with a test structure for detecting parasitic contact structures on the semiconductor wafer, in which a first interconnect plane (A) contains interconnects ( 1 ) running parallel to one another and a second interconnect ( 2 ) that is arranged between the latter. The two first interconnects ( 1 ) are connected by means of contact elements ( 4 ) arranged above them, to a third interconnect ( 3 ) that runs in a second interconnect plane (B) transverse to the first and second interconnects, and that also crosses the second interconnect ( 2 ). If there is a parasitic contact structure ( 5 ) formed between the contact elements ( 4 ), which has arisen during the lithographic exposure for producing the contact elements ( 4 ) on account of constructively interfering diffraction maxima, then this shorts the second interconnect ( 2 ) to the third interconnect ( 3 ). This results in a leakage current path perpendicular to the substrate surface (10a), the path extending from the second ( 2 ) to the third ( 3 ) interconnect even in the case of very narrow parasitic contact structures ( 5 ). When test needles are placed in contact with the second and third interconnects, an electrical measurement allows the extent of a parasitic contact structure ( 5 ) to be detected with a particularly high level of probability.

    4.
    发明专利
    未知

    公开(公告)号：DE10245533B4

    公开(公告)日：2007-11-08

    申请号：DE10245533

    申请日：2002-09-30

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： FELBER ANDREAS ,  ROSKOPF VALENTIN

    IPC: H01L27/108 ,  G11C29/50 ,  H01L21/66 ,  H01L21/8242 ,  H01L23/544 ,  H01L27/02

    Abstract: A test structure for a memory cell array determines a doping region of an electrode connection that, in a memory cell, connects an inner capacitor electrode of a trench capacitor to an associated selection transistor. The test structure has an electrical contact with a predetermined contact area disposed between a regular matrix configuration of four trench capacitors.

    5.
    发明专利
    未知

    公开(公告)号：DE10242054B3

    公开(公告)日：2004-04-15

    申请号：DE10242054

    申请日：2002-09-11

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： LACHENMANN SUSANNE ,  ROSKOPF VALENTIN ,  SUKMAN SIBINA ,  FELBER ANDREAS

    IPC: G11C29/02 ,  G11C29/50 ,  H01L21/8242 ,  H01L23/544 ,  G11C29/00

    Abstract: A test structure for determining the resistance of a conducting junction between an active region of a selection transistor and a storage capacitor in a matrix-type cell array where the active regions of the selection transistors are in rows in a first direction and the storage capacitors are in rows in a second direction running perpendicular to the first direction. The conducting junctions between the active regions of the selection transistors and the storage capacitors are formed at overlapping areas of the mutually perpendicular rows each in a single edge region of the overlapping area in the first direction. The active regions of the selection transistors and/or the storage capacitors are connected by tunnel structures or bridge structures in the second direction in the region adjoining the junction to be measured between the active region of the selection transistor and the storage capacitor. This achieves a low-impedance connection to the junction to be measured.

    6.
    发明专利
    未知

    公开(公告)号：DE102005003000B4

    公开(公告)日：2007-02-08

    申请号：DE102005003000

    申请日：2005-01-21

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： ROSKOPF VALENTIN ,  FELBER ANDREAS ,  LACHENMANN SUSANNE ,  SUKMAN-PRAEHOFER SIBINA

    IPC: H01L23/544 ,  H01L21/66 ,  H01L27/108

    Abstract: The product has a semiconductor substrate and a test structure with a transistor comprising two source and drain regions. The substrate comprises an isolation layer (13) that separates a gate electrode from the substrate. A dopant diffusion region (15) is arranged in the substrate and a capacitor electrode is connected with one of the source and drain regions. The dopant diffusion region is connected with the capacitor electrode. An independent claim is also included for a method of electrical measuring of a test structure of a semiconductor product.

    8.
    发明专利
    未知

    公开(公告)号：DE10245533A1

    公开(公告)日：2004-04-08

    申请号：DE10245533

    申请日：2002-09-30

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： FELBER ANDREAS ,  ROSKOPF VALENTIN

    IPC: G11C29/50 ,  H01L21/8242 ,  H01L23/544 ,  H01L27/02 ,  H01L27/108 ,  H01L21/66

    Abstract: A test structure for a memory cell array determines a doping region of an electrode connection that, in a memory cell, connects an inner capacitor electrode of a trench capacitor to an associated selection transistor. The test structure has an electrical contact with a predetermined contact area disposed between a regular matrix configuration of four trench capacitors.

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