公开(公告)号：DE10245534B4

公开(公告)日：2005-12-22

申请号：DE10245534

申请日：2002-09-30

Applicant: INFINEON TECHNOLOGIES AG

Inventor： FELBER ANDREAS ,  ROSKOPF VALENTIN

IPC: H01L21/8242 ,  H01L23/544 ,  H01L27/108 ,  H01L21/66

公开(公告)号：DE10254160A1

公开(公告)日：2004-06-09

申请号：DE10254160

申请日：2002-11-20

Applicant: INFINEON TECHNOLOGIES AG

Inventor： KOWALSKI BERNHARD ,  FELBER ANDREAS ,  ROSSKOPF VALENTIN ,  SCHLOESSER TILL ,  LINDOLF JUERGEN

IPC: H01L21/8242 ,  H01L27/02 ,  H01L27/108 ,  H01L29/94 ,  G11C11/40

Abstract: A transistor array has vertical FET transistors each connected to a storage capacitor of a memory cell array. Gate electrode strips, which form word lines, of the transistors are located on both sides of active webs running parallel to one another and are connected to a superimposed metal plane by word line or CS contacts. To insulate these word line contacts from the other elements of the transistor array and of the cell array, the word line contacts are located in deep trenches that are introduced into the webs.

公开(公告)号：DE10261457B3

公开(公告)日：2004-03-25

申请号：DE10261457

申请日：2002-12-31

Applicant: INFINEON TECHNOLOGIES AG

Inventor： KOWALSKI BERNHARD ,  FELBER ANDREAS ,  ROSSKOPF VALENTIN ,  SCHLOESSER TILL ,  LINDOLF JUERGEN

IPC: G11C29/02 ,  H01L21/8242 ,  H01L23/544 ,  H01L27/02 ,  H01L27/108 ,  H01L23/528 ,  G11C7/24

Abstract: The integrated circuit has a transistor array of vertical FET selection transistors and storage capacitors in deep trenches for an array of semiconducting cells associated with the transistor array, word lines and intersecting parallel bit lines. An array diagnosis test structure has first and second offset word line combs alternately connecting different word lines and first and second bit line combs alternately connecting different bit lines. The integrated circuit has a transistor array (11) of vertical FET selection transistors formed by active elements (121-12k) in the form of parallel vertical trenches in a substrate and storage capacitors in deep trenches for an array of semiconducting cells associated with the transistor array, word lines (131-13k) along the active elements and intersecting parallel bit lines (141-14m). An array diagnosis test structure contains first and second offset word line combs (20,21) alternately connecting different word lines and first and second bit line combs (30,31) alternately connecting different bit lines.

公开(公告)号：DE10254160B4

公开(公告)日：2006-07-20

申请号：DE10254160

申请日：2002-11-20

Applicant: INFINEON TECHNOLOGIES AG

Inventor： KOWALSKI BERNHARD ,  FELBER ANDREAS ,  ROSSKOPF VALENTIN ,  SCHLOESSER TILL ,  LINDOLF JUERGEN

IPC: H01L27/108 ,  G11C11/40 ,  H01L21/8242 ,  H01L27/02 ,  H01L29/94

Abstract: A transistor array has vertical FET transistors each connected to a storage capacitor of a memory cell array. Gate electrode strips, which form word lines, of the transistors are located on both sides of active webs running parallel to one another and are connected to a superimposed metal plane by word line or CS contacts. To insulate these word line contacts from the other elements of the transistor array and of the cell array, the word line contacts are located in deep trenches that are introduced into the webs.

公开(公告)号：DE10340714B3

公开(公告)日：2005-05-25

申请号：DE10340714

申请日：2003-09-04

Applicant: INFINEON TECHNOLOGIES AG

Inventor： ROSSKOPF VALENTIN ,  LACHENMANN SUSANNE ,  SUKMAN SIBINA ,  FELBER ANDREAS

IPC: G11C29/00 ,  G11C29/50 ,  H01L21/8242 ,  H01L23/544 ,  H01L31/0328

公开(公告)号：DE102005003000A1

公开(公告)日：2006-08-03

申请号：DE102005003000

申请日：2005-01-21

Applicant: INFINEON TECHNOLOGIES AG

Inventor： ROSKOPF VALENTIN ,  FELBER ANDREAS ,  LACHENMANN SUSANNE ,  SUKMAN-PRAEHOFER SIBINA

IPC: H01L23/544 ,  H01L21/66 ,  H01L27/108

Abstract: The product has a semiconductor substrate and a test structure with a transistor comprising two source and drain regions. The substrate comprises an isolation layer (13) that separates a gate electrode from the substrate. A dopant diffusion region (15) is arranged in the substrate and a capacitor electrode is connected with one of the source and drain regions. The dopant diffusion region is connected with the capacitor electrode. An independent claim is also included for a method of electrical measuring of a test structure of a semiconductor product.

公开(公告)号：DE10303963B4

公开(公告)日：2005-02-10

申请号：DE10303963

申请日：2003-01-31

Applicant: INFINEON TECHNOLOGIES AG

Inventor： KOWALSKI BERNHARD ,  FELBER ANDREAS ,  ROSSKOPF VALENTIN ,  LINDOLF JUERGEN ,  SCHLOESSER TILL ,  GOEBEL BERND

IPC: G11C29/50 ,  G11C29/00

Abstract: The integrated circuit has vertical FET transistors formed in deep channels [DT] as an array of devices. Also formed in the channels are diagonal capacitors. The structure has active semiconductor elements and a conducting strips [BS]. There are bit line contacts [CB] with inputs [E] and outputs [A].

公开(公告)号：DE10332312B3

公开(公告)日：2005-01-20

申请号：DE10332312

申请日：2003-07-16

Applicant: INFINEON TECHNOLOGIES AG

Inventor： FREY ULRICH ,  LINDOLF JUERGEN ,  FELBER ANDREAS

IPC: H01L23/525

Abstract: The integrated semiconductor circuit (20) has a programmable switch element (10) switched between an off state and an on state by supplying a positive programming voltage (V+) to a counter-electrode (5) of the switch element, separated from a substrate electrode (2) within a substrate (1) held at a substrate potential (Vo) via an insulation layer (8). The substrate electrode is supplied with a negative programming voltage (V-) during programming of the switch element, a current barrier layer (7) preventing a current flow between the substrate electrode and the substrate.

公开(公告)号：DE10303963A1

公开(公告)日：2004-08-19

申请号：DE10303963

申请日：2003-01-31

Applicant: INFINEON TECHNOLOGIES AG

Inventor： KOWALSKI BERNHARD ,  FELBER ANDREAS ,  ROSSKOPF VALENTIN ,  LINDOLF JUERGEN ,  SCHLOESSER TILL ,  GOEBEL BERND

IPC: G11C29/50 ,  G11C29/00

Abstract: The integrated circuit has vertical FET transistors formed in deep channels [DT] as an array of devices. Also formed in the channels are diagonal capacitors. The structure has active semiconductor elements and a conducting strips [BS]. There are bit line contacts [CB] with inputs [E] and outputs [A].

公开(公告)号：DE10245533B4

公开(公告)日：2007-11-08

申请号：DE10245533

申请日：2002-09-30

Applicant: INFINEON TECHNOLOGIES AG

Inventor： FELBER ANDREAS ,  ROSKOPF VALENTIN

IPC: H01L27/108 ,  G11C29/50 ,  H01L21/66 ,  H01L21/8242 ,  H01L23/544 ,  H01L27/02

Abstract: A test structure for a memory cell array determines a doping region of an electrode connection that, in a memory cell, connects an inner capacitor electrode of a trench capacitor to an associated selection transistor. The test structure has an electrical contact with a predetermined contact area disposed between a regular matrix configuration of four trench capacitors.