公开(公告)号：JP2002157874A

公开(公告)日：2002-05-31

申请号：JP2001253609

申请日：2001-08-23

Applicant: INFINEON TECHNOLOGIES AG

Inventor： GOGL DIETMAR ,  SCHLOSSER TILL

IPC: G11C11/14 ,  G11C11/15 ,  G11C11/16 ,  H01L21/8246 ,  H01L27/105 ,  H01L43/08

Abstract: PROBLEM TO BE SOLVED: To provide an MRAM arrangement in which a cross point structure having advantages of a transistor memory cell is present in common in all possible large areas. SOLUTION: TMR-memory cells 1 to 4 and 5 to 8 are interposed between a bit line BL and word lines WL1 and WL2, respectively. Memory cells 1 to 8 include an soft magnetic layer, a tunnel resistive layer, and a hard magnetic layer. The ends of the TMR-memory cells 1 to 4 and 5 to 8 are connected to the drains or the source of switching transistors Tr1 and Tr2, respectively. The gates of the switching transistors Tr1 and Tr2 are connected to the word lines WL1 and WL2, respectively. Four TMR-memory cells 1 to 4 or 5 to 8 are connected to one switching transistor Tr1 or Tr2, respectively.

公开(公告)号：JP2006054431A

公开(公告)日：2006-02-23

申请号：JP2005180338

申请日：2005-06-21

Applicant: Infineon Technologies Ag ,  インフィネオン テクノロジーズ アクチエンゲゼルシャフト

Inventor： WEIS ROLF ,  SCHLOSSER TILL ,  SCHWERIN ULRIKE GRUNING VON

IPC: H01L21/8242 ,  H01L27/108 ,  H01L29/78

Abstract: PROBLEM TO BE SOLVED: To achieve a high degree of integration in forming a trenched DRAM memory cell by facilitating the connection between a vertical transistor and a trench capacitor. SOLUTION: A first and a second source/drain regions, a channel region disposed in a semiconductor substrate for connecting the first and the second source/drain regions, and a gate electrode are included; and the gate electrode is disposed along the channel region for controlling the current flowing between the first and the second source/drain regions and is electrically insulated from the channel region. Further, in the channel region, the channel has a ridge-shaped fin region. Here, the "ridge" consists of a single upper surface and two side surfaces perpendicular to the line connecting the first source/drain region and the second source/drain region (in the cross-sectional view). This upper surface is disposed below the surface of the semiconductor substrate, and the gate electrode is provided along this upper surface and the two side surfaces. COPYRIGHT: (C)2006,JPO&NCIPI

Abstract translation: 要解决的问题：通过促进垂直晶体管和沟槽电容器之间的连接来实现形成沟槽DRAM存储单元的高集成度。 解决方案：包括第一和第二源极/漏极区域，设置在用于连接第一和第二源极/漏极区域的半导体衬底中的沟道区域和栅极电极; 并且栅极电极沿着沟道区域设置，用于控制在第一和第二源极/漏极区域之间流动的电流，并且与沟道区域电绝缘。 此外，在通道区域中，通道具有脊形翅片区域。 这里，“脊”由垂直于连接第一源极/漏极区域和第二源极/漏极区域的线的单个上表面和两个侧表面（在横截面图中）组成。 该上表面设置在半导体衬底的表面下方，并且栅电极沿着该上表面和两个侧表面设置。 版权所有（C）2006，JPO＆NCIPI

公开(公告)号：JP2001291848A

公开(公告)日：2001-10-19

申请号：JP2001068253

申请日：2001-03-12

Applicant: INFINEON TECHNOLOGIES AG

Inventor： FREY ALEXANDER ,  WEBER WERNER ,  SCHLOSSER TILL

IPC: H01L27/108 ,  G11C11/407 ,  G11C11/4097 ,  H01L21/8242 ,  H01L27/02

Abstract: PROBLEM TO BE SOLVED: To decrease an area of a DRAM memory cell. SOLUTION: A memory cell 51 has at least a memory capacitor 52 and a selection transistor 12 which are intrinsically formed in a region of a rectangular cell region 59. The rectangular cell region 59 has a larger range in a longitudinal direction L than in a widthwise direction B. It is wired to a periphery of a cell via word lines 56, 57 and a bit line 55, or can be wired thereto. The word lines 56, 57 and the bit line 55 are transmitted onto the memory cell 51 and are directed at least intrinsically perpendicular to each other.