公开(公告)号：JP2002124080A

公开(公告)日：2002-04-26

申请号：JP2001235533

申请日：2001-08-02

Applicant: INFINEON TECHNOLOGIES AG

Inventor： GOGL DIETMAR ,  KANDOLF HELMUT ,  LAMMERS STEFAN

IPC: G11C11/14 ,  G11C5/06 ,  G11C11/15 ,  G11C11/16 ,  H01L21/8246 ,  H01L27/105 ,  H01L43/08

Abstract: PROBLEM TO BE SOLVED: To provide a device performing write-in in which loss of MRAM is less and in which memory cells having large resistance, short word lines and/or bit lines are not utilized. SOLUTION: This device has many memory cells (Z0, Z1, etc.), and these memory cells are provided respectively in a memory cell field between a word line(WL) and bit lines (BL, BL0, BL1, etc.). At the time of write-in process for the prescribed memory cell, voltage drop (V1-V2) is caused in the selected word line(WL) connected to this memory cell. When voltage V1 or voltage V2

公开(公告)号：JP2002134708A

公开(公告)日：2002-05-10

申请号：JP2001211245

申请日：2001-07-11

Applicant: INFINEON TECHNOLOGIES AG

Inventor： GOGL DIETMAR ,  ROEHR THOMAS ,  HOENIGSCHMID HEINZ

IPC: G11C11/14 ,  G11C7/18 ,  G11C11/15 ,  G11C11/16 ,  H01L21/8246 ,  H01L27/105 ,  H01L27/22 ,  H01L43/08

Abstract: PROBLEM TO BE SOLVED: To reduce nonconforming action caused by overcoupling among the adjacent lines in a memory matrix, comprising a cell field composed of row lines and column lines in which the memory elements are situated at each point, where the row lines and column lines intersect one another, and the column line and/or row lines of the cell field are placed adjacent to each other. SOLUTION: This memory matrix is constituted, such that the order of row lines or column lines are equal in the edges of the memory matrix counterposed to each other regarding changes in the configurational constitution of the lines. As a result of this, additional circuit cost for executing address decoding, namely an additional circuit cost generated when an address line is not assigned correspondingly or it has a different order from the original order is avoided. For the case of MRAM, the connection constitution of the row lines and column lines in both edges of a cell field becomes advantageous. Furthermore, the cell field or its row lines and/or column line is made symmetrical by a mirror image, regarding changes in their arrangement constitution.

公开(公告)号：JP2002093144A

公开(公告)日：2002-03-29

申请号：JP2001197558

申请日：2001-06-28

Applicant: INFINEON TECHNOLOGIES AG

Inventor： BOEHM THOMAS ,  GOGL DIETMAR ,  MUELLER GERHARD ,  LOEER THOMAS

IPC: G11C11/14 ,  G11C7/12 ,  G11C11/15 ,  G11C11/16 ,  H01L21/8246 ,  H01L27/10 ,  H01L27/105 ,  H01L43/08

Abstract: PROBLEM TO BE SOLVED: To provide a current driver arrangement capable of supplying a large current at a low voltage when the area needs to be small. SOLUTION: In a current driver arrangement described in the above, this problem can be solved by configuring a driver of an n-type field effect transistor and a current source connected in series therewith. Concretely, a current driver arrangement for an MRAM is provided comprising a memory cell field having a plurality of memory cells (Z) at the crossing position of a word line (WL) and a bit line (BL), and drivers (T1, T2) supplied to each end of the above word line (WL) and the above bit line (BL), and allocated to the above word line (WL) and the above bit line (BL).

公开(公告)号：JP2002203388A

公开(公告)日：2002-07-19

申请号：JP2001331484

申请日：2001-10-29

Applicant: INFINEON TECHNOLOGIES AG

Inventor： FREITAG MARTIN ,  LAMMERS STEFAN ,  GOGL DIETMAR ,  ROEHR THOMAS

IPC: G11C11/14 ,  G11C11/15 ,  G11C11/16 ,  H01L21/8246 ,  H01L27/105 ,  H01L27/22 ,  H01L43/08

Abstract: PROBLEM TO BE SOLVED: To provide a method for obstructing undesirable programming in a MRAM device so that disablement of programming owing to scattered magnetic field of a memory cell being adjacent to a selection memory cell can be surely and simply obstructed. SOLUTION: A current IBL2 flowing in a bit line BL2 generates a scattered magnetic field in a MTJ memory cell I3 in an intersection part of a bit line BL3 and a word line WL1. Then an adequate compensation current IBL3 is made to flow in the bit line BL3 to suppress influence of this scattered magnetic field, scattered magnetic field in the MTJ memory cell I3 can be canceled by compensation magnetic field generated by this compensation current IBL3.

公开(公告)号：JP2002164515A

公开(公告)日：2002-06-07

申请号：JP2001275812

申请日：2001-09-11

Applicant: INFINEON TECHNOLOGIES AG

Inventor： BOEHM THOMAS ,  GOGL DIETMAR ,  FREITAG MARTIN ,  LAMMERS STEFAN

IPC: G11C11/14 ,  G11C5/02 ,  G11C11/15 ,  G11C11/16 ,  H01L21/8246 ,  H01L27/10 ,  H01L27/105 ,  H01L27/22 ,  H01L43/08

Abstract: PROBLEM TO BE SOLVED: To provide an MRAM module structure wherein high packing density of memory cell sections is achieved. SOLUTION: This MRAM module structure is constituted of a plurality of memory cell sections (A, P). The respective memory cell sections (A, P) are constituted of memory arrays (A) having a plurality of memory cells (WML, TL, HML) and peripheral circuits (P) surrounding edges of the memory arrays (A). The peripheral circuits (P) surround the memory arrays (A) in such a manner that the respective memory cell sections (A, P) have a cross structure in a plane, essentially. The memory cell sections (A, P) are so nested in each other that the memory cell sections (A, P) are offset mutually on individual rows (1, 2, 3).

公开(公告)号：JP2002157874A

公开(公告)日：2002-05-31

申请号：JP2001253609

申请日：2001-08-23

Applicant: INFINEON TECHNOLOGIES AG

Inventor： GOGL DIETMAR ,  SCHLOSSER TILL

IPC: G11C11/14 ,  G11C11/15 ,  G11C11/16 ,  H01L21/8246 ,  H01L27/105 ,  H01L43/08

Abstract: PROBLEM TO BE SOLVED: To provide an MRAM arrangement in which a cross point structure having advantages of a transistor memory cell is present in common in all possible large areas. SOLUTION: TMR-memory cells 1 to 4 and 5 to 8 are interposed between a bit line BL and word lines WL1 and WL2, respectively. Memory cells 1 to 8 include an soft magnetic layer, a tunnel resistive layer, and a hard magnetic layer. The ends of the TMR-memory cells 1 to 4 and 5 to 8 are connected to the drains or the source of switching transistors Tr1 and Tr2, respectively. The gates of the switching transistors Tr1 and Tr2 are connected to the word lines WL1 and WL2, respectively. Four TMR-memory cells 1 to 4 or 5 to 8 are connected to one switching transistor Tr1 or Tr2, respectively.

公开(公告)号：JP2002133855A

公开(公告)日：2002-05-10

申请号：JP2001241347

申请日：2001-08-08

Applicant: INFINEON TECHNOLOGIES AG

Inventor： BOEHM THOMAS ,  ROEHR THOMAS ,  GOGL DIETMAR

IPC: G11C11/14 ,  G11C8/08 ,  G11C8/10 ,  G11C11/15 ,  G11C11/16 ,  H01L21/8246 ,  H01L27/10 ,  H01L27/105 ,  H01L43/08

Abstract: PROBLEM TO BE SOLVED: To reduce the complexity and occupancy area of wirings in a driver circuit for word lines of a memory matrix. SOLUTION: In the electronic driver circuit for the word lines WL in the memory matrix 3, a driver source 2, for example, coded output sides IV0-IV3 of a current/voltage source are connected to selected word lines WLi-2-WLi+1. In this case, the word lines WL are selected for every block by control signals SLNP, SLN1, SLN2, and the outputs of the driver source 2 are applied to them. In that case, each activated word line WLi is selected by the coding of the driver source 2.

公开(公告)号：WO0239454A3

公开(公告)日：2002-12-19

申请号：PCT/EP0112622

申请日：2001-10-31

Applicant: INFINEON TECHNOLOGIES AG ,  FREITAG MARTIN ,  HOENIGSCHMID HEINZ ,  GOGL DIETMAR ,  LAMMERS STEFAN

Inventor： FREITAG MARTIN ,  HOENIGSCHMID HEINZ ,  GOGL DIETMAR ,  LAMMERS STEFAN

IPC: H01L27/105 ,  G11C11/16 ,  H01L21/8246 ,  H01L27/22 ,  H01L43/08 ,  G11C11/15

CPC classification number: H01L27/222 ,  B82Y10/00 ,  G11C11/16

Abstract: The form of the supply lines in a cell field made from a matrix of columned and lined supply lines of a plurality of magnetic memory cells is optimised by diverging from a quadratic cross-section of the supply lines so that the magnetic field component Bx of the writing currents arranged on the plane of the cell field is rapidly reduced at an increasing distance from the increasing point of intersection.

Abstract translation: 从列和行的矩阵一个建成的引线的形状导致的多个磁存储单元的单元阵列被偏离引线的方形横截面的优化，使得磁场分量从交叉点Bx的随着距离的增加躺在单元阵列平面中的写电流的足够快地 降低。

公开(公告)号：WO02073618A3

公开(公告)日：2003-05-01

申请号：PCT/DE0200897

申请日：2002-03-13

Applicant: INFINEON TECHNOLOGIES AG ,  GOGL DIETMAR ,  VIEHMANN HANS-HEINRICH

Inventor： GOGL DIETMAR ,  VIEHMANN HANS-HEINRICH

IPC: G11C11/15 ,  G11C7/06 ,  G11C11/16

CPC classification number: G11C7/067 ,  G11C7/062 ,  G11C2207/063

Abstract: A memory sense amplifier (10) for a semiconductor memory device (1) is provided with a compensation current source device (30) which generates a compensation current (Icomp) and feeds it to an interconnected bit line (4). Said compensation current (Icomp) is selected in such a manner that during readout a potential gradient can be generated and/or maintained in cooperation with a compensation voltage source device (20) on the selected and interlinked bit line device (4) that is substantially constant over time.

Abstract translation: 在读出放大器装置（10），用于半导体存储器设备（1）是一个补偿电流源装置（30）设置，通过它可产生一个补偿电流（ICOMP），并且可以提供相关联的位线（4），所述补偿电流（ICOMP）被选择，使得当 是（4）具有可以产生预期的补偿电压源装置（20）到所选择的和连接的位线大致时间上恒定的电势差和/或维持耐久性合作公吨读取操作。

公开(公告)号：WO02084705A3

公开(公告)日：2003-05-01

申请号：PCT/DE0201255

申请日：2002-04-05

Applicant: INFINEON TECHNOLOGIES AG ,  GOGL DIETMAR ,  SCHLOESSER TILL

Inventor： GOGL DIETMAR ,  SCHLOESSER TILL

IPC: G11C11/15 ,  H01L21/8246 ,  H01L27/105 ,  H01L43/08

CPC classification number: G11C11/15

Abstract: The invention relates to a method for operating an MRAM semiconductor memory arrangement, whereby, in order to read stored information, reversible magnetic changes are carried out on the TMR cells (TMR1, TMR2, ...) and a corresponding transient changed current compared with the original read signal. The TMR memory cell itself can thus serve as reference, although the information in the TMR memory cell is not destroyed, in other words the same must not be back-written. The invention is used to advantage in an MRAM memory arrangement, in which several TMR cells (TMR1, ..., TMR4) are connected in parallel to a selection transistor (TR1) and in which a write line (WL1, WL2), not electrically connected to the memory cell, is provided.

Abstract translation: 在用于读取到TMR细胞（TMR1，TMR2，...）存储的信息可逆磁变化操作MRAM半导体存储器件本发明的方法被执行，并且其结果是简要地改变流与原始读信号相比较。 其特征在于所述TMR存储单元本身可以作为参考，虽然信息是在TMR存储单元不被破坏，即 它不能被恢复。 本发明优选适用于MRAM存储器布置，其中多个TMR单元（TMR1，...，TMR4）平行于选择晶体管（TR1）被连接，并且在其中写入线没有电连接到存储单元（WL1，WL2 ）是否存在。