公开(公告)号：DE102005031643A1

公开(公告)日：2007-02-01

申请号：DE102005031643

申请日：2005-07-06

Applicant: INFINEON TECHNOLOGIES AG

Inventor： SCHNIEDER RALF

IPC: G11C11/4076 ,  G11C7/22

Abstract: A DRAM memory comprises a memory cell bank comprised of memory cells being activated by means of internal row and column access instructions, a command decoder generating, dependent on an external memory access instruction, at least one column access instruction within a first and at least one row access instruction within a second decoding time, and a clock signal delay circuit for delaying an external clock signal with the first decoding time for generating an internal column clock signal and for delaying the external clock signal with the second decoding time for generating an internal row clock signal. Each memory cell bank comprises an associated APC counter for delaying a column access instruction with autoprecharge. Each of the column access instructions are respectively delayed by an associated shift register being clocked by the internal column clock signal for generating the internal column access instructions. The APC counter is clocked by the internal row clock signal and delays each of the column access instructions in accordance with an associated programmable count for producing an internal autoprecharge instruction for the associated memory cell bank.

公开(公告)号：DE102005031643B4

公开(公告)日：2007-06-14

申请号：DE102005031643

申请日：2005-07-06

Applicant: INFINEON TECHNOLOGIES AG

Inventor： SCHNIEDER RALF

IPC: G11C11/4076 ,  G11C7/22

Abstract: A DRAM memory comprises a memory cell bank comprised of memory cells being activated by means of internal row and column access instructions, a command decoder generating, dependent on an external memory access instruction, at least one column access instruction within a first and at least one row access instruction within a second decoding time, and a clock signal delay circuit for delaying an external clock signal with the first decoding time for generating an internal column clock signal and for delaying the external clock signal with the second decoding time for generating an internal row clock signal. Each memory cell bank comprises an associated APC counter for delaying a column access instruction with autoprecharge. Each of the column access instructions are respectively delayed by an associated shift register being clocked by the internal column clock signal for generating the internal column access instructions. The APC counter is clocked by the internal row clock signal and delays each of the column access instructions in accordance with an associated programmable count for producing an internal autoprecharge instruction for the associated memory cell bank.

公开(公告)号：DE102005020055A1

公开(公告)日：2006-11-09

申请号：DE102005020055

申请日：2005-04-29

Applicant: INFINEON TECHNOLOGIES AG

Inventor： SCHAMBERGER FLORIAN ,  SCHNIEDER RALF

IPC: G11C29/52 ,  G11C17/18

Abstract: The module has a data bit buffer (2A-0) for buffering a data bit to be stored, where the data bit is copied into a data bit buffer (2B-0). An electrically programmable fuse component is burned according to the buffered data bit and is overwritten onto one of the two data bit buffers depending on a logical condition of the burned fuse component. A comparison logic (2D-0) compares the data bit buffered in the overwritten data bit buffer with the data bit buffered in the other data bit buffer for verifying, whether the burning of the fuse component takes place in an error-free manner. An independent claim is also included for a method for durable and secure storage of a data bit in an electrically programmable fuse component.