公开(公告)号：DE10341321A1

公开(公告)日：2005-04-14

申请号：DE10341321

申请日：2003-09-08

Applicant: INFINEON TECHNOLOGIES AG

Inventor： SCHROEDER PAUL ,  GOLDBACH MATTHIAS ,  MONO TOBIAS

IPC: H01L21/027 ,  H01L21/033 ,  H01L21/302 ,  H01L21/308 ,  H01L21/461 ,  H01L21/8236 ,  H01L21/8246 ,  H01L21/8247

Abstract: The production of a trench (26) in a layer or layer stack (102-104) on a semiconductor wafer comprises preparing a semiconductor wafer with a mask layer (12) and a photo-sensitive resist (16), exposing the resist and developing to form a resist web, implanting a first part of the mask layer with doping particles, removing the web, dissolving the second non-implanted part of the mask layer to form an opening in the mask layer, and anisotropically etching the layer or layer stack selectively to the mask layer to transfer the opening into the layer or layer stack to form the trench.

公开(公告)号：DE10255626A1

公开(公告)日：2004-06-17

申请号：DE10255626

申请日：2002-11-28

Applicant: INFINEON TECHNOLOGIES AG

Inventor： SCHROEDER PAUL ,  MONO TOBIAS

IPC: G06F17/50 ,  H01L21/768 ,  H01L27/02 ,  H03K19/00

公开(公告)号：DE102004055248B3

公开(公告)日：2006-03-02

申请号：DE102004055248

申请日：2004-11-16

Applicant: INFINEON TECHNOLOGIES AG

Inventor： SCHROEDER PAUL ,  SCHACHT JOCHEN

IPC: G03F7/20 ,  H01L21/768

Abstract: In order to form a contact in a layer on a substrate, in particular a contact in a logic circuit in a semiconductor component, the mask layer is structured for etching of the contact holes with a photoresist layer which is exposed using two masks, with the first mask containing a regular pattern of contact structures with a period which corresponds to the order of magnitude of twice the edge length of the contact hole, and with the second mask containing a pattern with a structure which surrounds at least the contact hole area, and thus covers it.

公开(公告)号：DE10246830A1

公开(公告)日：2004-02-12

申请号：DE10246830

申请日：2002-10-08

Applicant: INFINEON TECHNOLOGIES AG

Inventor： SCHROEDER PAUL ,  SCHEDEL THORSTEN

IPC: H01L21/768 ,  H01L27/04

Abstract: Production of a wiring surface on a semiconductor wafer (1) comprises: (a) applying a first insulating layer on a wafer; (b) structuring the layer to form strip conductor trenches in the layer; (c) depositing a first barrier layer (4); (d) depositing a start layer (5) to form a core for a copper layer; (e) sputtering or depositing a copper layer (6); (f) polishing the copper layer up to the surface of the trenches; (g) depositing a second barrier layer (7); (h) removing the first insulating layer between the trenches; and (i) filling the exposed regions between the strip conductors with a second insulating layer (8). An empty chamber is formed in the second insulating layer in the filled regions between the copper strip conductors. An Independent claim is also included for a semiconductor component formed by the above process.