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    IMPROVED STRAP RESISTANCE USING SELECTIVE OXIDATION TO CAP DT POLY BEFORE STI ETCH
    1.
    发明申请
    IMPROVED STRAP RESISTANCE USING SELECTIVE OXIDATION TO CAP DT POLY BEFORE STI ETCH 审中-公开
    使用选择性氧化处理改善抗菌性能，提高抗菌性能

    公开(公告)号：WO03017356A3

    公开(公告)日：2003-08-28

    申请号：PCT/EP0209009

    申请日：2002-08-12

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： WENSLEY PAUL ,  COMMONS MARTIN ,  MONO TOBIAS ,  KLEE VEIT

    IPC: H01L21/762 ,  H01L21/763 ,  H01L21/8242

    CPC classification number: H01L27/10864 ,  H01L21/76224 ,  H01L21/763 ,  H01L27/10861

    Abstract: A method of providing shallow trench (143) isolation for a semiconductor wafer (100). Trenches (113) are formed within a first semiconductor material (112) and a pad nitride (114), leaving a portion of first semiconductor material (112) and pad nitride (114) in a region between the trenches (113). A second semiconductor material (116) is deposited over the trenches (113) to fill the trenches (113) to a height below the first semiconductor material (112) top surface. A first insulator (130) is selectively formed over the second semiconductor material (116). The pad nitride (114) and a portion of the first semiconductor material (112) between the trenches (113) are removed to isolate element regions of the wafer (100) and form straps (142) having a low resistance.

    Abstract translation: 一种为半导体晶片（100）提供浅沟槽（143）隔离的方法。 在第一半导体材料（112）和焊盘氮化物（114）内形成沟槽（113），在沟槽（113）之间的区域中留下第一半导体材料（112）和焊盘氮化物（114）的一部分。 在沟槽（113）上沉积第二半导体材料（116）以将沟槽（113）填充到第一半导体材料（112）顶表面下方的高度。 第一绝缘体（130）选择性地形成在第二半导体材料（116）上方。 焊盘氮化物（114）和沟槽（113）之间的第一半导体材料（112）的一部分被去除以隔离晶片（100）的元件区并且形成具有低电阻的带（142）。

    DUMMY PATTERNS FOR REDUCING PROXIMITY EFFECTS AND METHOD OF USING SAME
    2.
    发明申请
    DUMMY PATTERNS FOR REDUCING PROXIMITY EFFECTS AND METHOD OF USING SAME 审中-公开
    用于减少邻近效应的虚拟模式和使用该模式的方法

    公开(公告)号：WO2004027519A3

    公开(公告)日：2004-09-23

    申请号：PCT/EP0309879

    申请日：2003-09-05

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： COMMONS MARTIN ,  KLEE VEIT ,  MONO TOBIAS ,  WENSLEY PAUL

    IPC: G03F1/00 ,  G03F1/36 ,  G03F1/14

    CPC classification number: G03F1/36

    Abstract: Disclosed is an optical lithographic mask having one or more dummy patterns, each said dummy pattern having a masked area of said optical lithographic mask seperated from one or more feature masked areas on said optical lithographic mask by an unmasked region of width d, wherein said width d is selected to substantially minimize an average deviation between the dimensions of said feature masked areas and corresponding features etched out upon a semiconductor surface utilizing said optical lithographic mask.

    Abstract translation: 公开了一种具有一个或多个虚设图案的光刻掩模，每个所述虚设图案具有所述光刻掩模的掩模区域，所述掩模区域与所述光刻掩模上的一个或多个特征掩模区域隔开宽度为d的未掩模区域， 选择d以基本上最小化所述特征掩模区域的尺寸与利用所述光刻掩模在半导体表面上蚀刻出的对应特征之间的平均偏差。

    3.
    发明专利
    未知

    公开(公告)号：DE60141602D1

    公开(公告)日：2010-04-29

    申请号：DE60141602

    申请日：2001-11-29

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： SCHROEDER UWE PAUL ,  MONO TOBIAS

    IPC: G02B5/30 ,  G03F7/20 ,  H01L21/027

    Abstract: A plate 50 for projection lithography comprising a first opaque region 54 located at the center of the plate 50 and a second opaque region 56 formed at the outer edge 52 of the plate. The first and second opaque regions define a light transmissive annular region 58. The annular region 58 comprises a first light transmissive area 60, 62 that imparts a first phase shift to light passing therethrough and a second light transmissive area 64, 66, which imparts a second phase shift to light passing therethrough.

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