公开(公告)号：JP2011066433A

公开(公告)日：2011-03-31

申请号：JP2010242271

申请日：2010-10-28

Applicant: Infineon Technologies Ag ,  インフィネオン テクノロジーズ アクチエンゲゼルシャフト

Inventor： LUAN HONGFA ,  SCHULZ THOMAS

IPC: H01L21/8238 ,  H01L21/8234 ,  H01L27/08 ,  H01L27/088 ,  H01L27/092 ,  H01L29/423 ,  H01L29/49 ,  H01L29/786

CPC classification number: H01L27/1211 ,  H01L21/823821 ,  H01L21/823842 ,  H01L21/823857 ,  H01L21/845 ,  H01L29/66803 ,  H01L29/785

Abstract: PROBLEM TO BE SOLVED: To provide improved structures of a plurality of transistors and manufacturing processes thereof.
SOLUTION: A complimentary metal oxide semiconductor (CMOS) device 100 includes a PMOS transistor having at least two first gate electrodes each having a first parameter, and an NMOS transistor having at least two second gate electrodes each having a second parameter, wherein the second parameter is different from the first parameter. The first parameter and the second parameter may include the thickness or the dopant profile of the gate electrode materials 120 of the PMOS and NMOS transistors. The first and second parameters of the at least two first gate electrodes and the at least two second gate electrodes define the work function of the PMOS and NMOS transistors, respectively.
COPYRIGHT: (C)2011,JPO&INPIT

Abstract translation: 要解决的问题：提供多个晶体管的改进的结构及其制造工艺。 解决方案：互补的金属氧化物半导体（CMOS）器件100包括PMOS晶体管，其具有至少两个具有第一参数的第一栅电极和具有至少两个具有第二参数的至少两个第二栅电极的NMOS晶体管，其中 第二个参数与第一个参数不同。 第一参数和第二参数可以包括PMOS和NMOS晶体管的栅电极材料120的厚度或掺杂物分布。 至少两个第一栅电极和至少两个第二栅电极的第一和第二参数分别定义了PMOS和NMOS晶体管的功函数。 版权所有（C）2011，JPO＆INPIT

公开(公告)号：JP2007123867A

公开(公告)日：2007-05-17

申请号：JP2006267833

申请日：2006-09-29

Applicant: Infineon Technologies Ag ,  インフィネオン テクノロジーズ アクチエンゲゼルシャフト

Inventor： LUAN HONGFA ,  SCHULZ THOMAS

IPC: H01L21/8238 ,  H01L27/08 ,  H01L27/092 ,  H01L29/423 ,  H01L29/49 ,  H01L29/786

CPC classification number: H01L27/1211 ,  H01L21/823821 ,  H01L21/823842 ,  H01L21/823857 ,  H01L21/845 ,  H01L29/66803 ,  H01L29/785

Abstract: PROBLEM TO BE SOLVED: To provide a manufacturing method for forming a plurality of gate electrodes with adjusted work functions. SOLUTION: A complementary metal oxide semiconductor (CMOS) device has: a PMOS transistor provided with at least two first gate electrodes 120 having a first parameter; and an NMOS transistor provided with at least two second gate electrodes 120 having a second parameter that is different from the first parameter. The first parameter and the second parameter comprise the thickness or the dopant profile of the gate electrode materials of the PMOS and NMOS transistors. The first and second parameters of at least two first gate electrodes and two second gate electrodes prescribe the work functions of the PMOS and the NMOS transistors, respectively. COPYRIGHT: (C)2007,JPO&INPIT

Abstract translation: 要解决的问题：提供一种用于形成具有调节功函数的多个栅电极的制造方法。 解决方案：互补金属氧化物半导体（CMOS）器件具有：具有至少两个具有第一参数的第一栅电极120的PMOS晶体管; 以及NMOS晶体管，其具有至少两个具有不同于第一参数的第二参数的第二栅电极120。 第一参数和第二参数包括PMOS和NMOS晶体管的栅电极材料的厚度或掺杂物分布。 至少两个第一栅电极和两个第二栅电极的第一和第二参数分别规定了PMOS和NMOS晶体管的功函数。 版权所有（C）2007，JPO＆INPIT

公开(公告)号：JP2007110091A

公开(公告)日：2007-04-26

申请号：JP2006238994

申请日：2006-09-04

Applicant: Infineon Technologies Ag ,  インフィネオン テクノロジーズ アクチエンゲゼルシャフト

Inventor： LUAN HONGFA ,  SCHULZ THOMAS

IPC: H01L21/8238 ,  H01L21/28 ,  H01L27/092 ,  H01L29/423 ,  H01L29/49 ,  H01L29/78 ,  H01L29/786

CPC classification number: H01L29/4966 ,  H01L21/28088 ,  H01L21/823842 ,  H01L27/0922 ,  H01L27/1203 ,  H01L29/513 ,  H01L29/517

Abstract: PROBLEM TO BE SOLVED: To provide a metal gate electrode having a work function suitable for CMOS (Complementary Metal-Oxide Semiconductor) device designing.
SOLUTION: Transistors and method of manufacturing them are disclosed. A complimentary metal oxide semiconductor (CMOS) device includes a PMOS (P-Channel Metal-Oxide Semiconductor) transistor having a first gate electrode comprising a first thickness, and an NMOS (N-Channel Metal-Oxide Semiconductor) transistor having a second gate electrode comprising a second thickness. The first thickness is greater than the second thickness. The first gate electrode and the second gate electrode preferably comprise the same material, and may comprise TiSiN, TaN, or TiN, as examples. The thickness of the first gate electrode and the second gate electrode set the work function of the PMOS and NMOS transistors.
COPYRIGHT: (C)2007,JPO&INPIT

Abstract translation: 要解决的问题：提供具有适用于CMOS（互补金属氧化物半导体）器件设计的功函数的金属栅电极。 解决方案：公开了晶体管及其制造方法。 互补金属氧化物半导体（CMOS）器件包括具有第一厚度的第一栅电极和具有第二栅电极的NMOS（N沟道金属氧化物半导体）晶体管的PMOS（P沟道金属氧化物半导体）晶体管 包括第二厚度。 第一厚度大于第二厚度。 第一栅电极和第二栅电极优选地包括相同的材料，并且可以包括TiSiN，TaN或TiN，作为实例。 第一栅电极和第二栅电极的厚度设置PMOS和NMOS晶体管的功函数。 版权所有（C）2007，JPO＆INPIT

公开(公告)号：WO2007057357A2

公开(公告)日：2007-05-24

申请号：PCT/EP2006068343

申请日：2006-11-10

Applicant: INFINEON TECHNOLOGIES AG ,  LI HONG-JYH ,  SCHULZ THOMAS

Inventor： LI HONG-JYH ,  SCHULZ THOMAS

IPC: H01L21/8238 ,  H01L21/336 ,  H01L21/84 ,  H01L27/12 ,  H01L29/49 ,  H01L29/786

CPC classification number: H01L21/823857 ,  H01L21/823821 ,  H01L21/845 ,  H01L27/1211 ,  H01L29/4908 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/78645

Abstract: Semiconductor devices with transistors having different gate dielectric materials and methods of manufacture thereof are disclosed. One embodiment includes a semiconductor device including a workpiece, the workpiece including a first region and a second region proximate the first region. A first transistor is disposed in the first region of the workpiece, the first transistor having at least two first gate electrodes. A first gate dielectric is disposed proximate each of the at least two first gate electrodes, the first gate dielectric comprising a first material. A second transistor is disposed in the second region of the workpiece, the second transistor having at least two second gate electrodes. A second gate dielectric is disposed proximate each of the at least two second gate electrodes, the second gate dielectric comprising a second material. The second material is different than the first material.

Abstract translation: 公开了具有不同栅介电材料的晶体管的半导体器件及其制造方法。 一个实施例包括包括工件的半导体器件，所述工件包括第一区域和靠近第一区域的第二区域。 第一晶体管设置在工件的第一区域中，第一晶体管具有至少两个第一栅电极。 第一栅极电介质设置在所述至少两个第一栅电极中的每一个附近，所述第一栅极电介质包括第一材料。 第二晶体管设置在工件的第二区域中，第二晶体管具有至少两个第二栅电极。 第二栅极电介质设置在所述至少两个第二栅电极中的每一个附近，所述第二栅极电介质包括第二材料。 第二种材料与第一种材料不同。

公开(公告)号：WO2004023557A3

公开(公告)日：2004-09-10

申请号：PCT/EP0309296

申请日：2003-08-21

Applicant: INFINEON TECHNOLOGIES AG ,  HOFMANN FRANZ ,  LANDGRAF ERHARD ,  LUYKEN RICHARD JOHANNES ,  SCHULZ THOMAS ,  SPECHT MICHAEL

Inventor： HOFMANN FRANZ ,  LANDGRAF ERHARD ,  LUYKEN RICHARD JOHANNES ,  SCHULZ THOMAS ,  SPECHT MICHAEL

IPC: H01L21/20 ,  H01L21/28 ,  H01L21/336 ,  H01L21/8246 ,  H01L27/10 ,  H01L27/115 ,  H01L29/73 ,  H01L29/76 ,  H01L29/792

CPC classification number: H01L29/7926 ,  H01L21/28282 ,  H01L27/115 ,  H01L27/11568 ,  H01L29/66833 ,  H01L29/792 ,  H01L29/7923

Abstract: The invention relates to a semiconductor memory with a number of memory cells, whereby each of the memory cells comprises four vertical memory transistors with trapping layers. The shallower contact regions are embodied in a semiconductor region running at an angle to the lines and gaps of the cell field, whereby the gate electrode preferably runs on the stage lateral surfaces of the shallower semiconductor region. A memory density of 1-2F per bit may thus be achieved.

Abstract translation: 本发明涉及具有多个存储单元的半导体存储器，每个存储单元包括具有俘获层的四个垂直存储晶体管。 较高的接触区形成在倾斜于单元阵列的行和列延伸的较高半导体区中，其中栅电极优选在较高半导体区的阶梯侧表面上被引导。 以这种方式可以实现每比特1-2F 2的存储密度。

公开(公告)号：WO03015182A3

公开(公告)日：2003-08-07

申请号：PCT/DE0202760

申请日：2002-07-26

Applicant: INFINEON TECHNOLOGIES AG ,  HOFMANN FRANZ ,  KRETZ JOHANNES ,  ROESNER WOLFGANG ,  SCHULZ THOMAS

Inventor： HOFMANN FRANZ ,  KRETZ JOHANNES ,  ROESNER WOLFGANG ,  SCHULZ THOMAS

IPC: H01L21/336 ,  H01L29/786

CPC classification number: H01L29/785 ,  H01L29/66795

Abstract: The invention relates to a fin field effect transistor that comprises a substrate, a fin structure above the substrate, as well as a drain region and a source region outside the fin structure above the substrate. The fin structure serves as a channel between the source region and the drain region. Source and drain region are formed once the gate has been produced.

Abstract translation: 鳍状场效应晶体管包括：基板;所述基板上的脊，和一个漏区和脊到基板以外的源极区。 脊用作源极区和漏极区之间的沟道。 源极和漏极区域中的栅极的形成之后形成。

公开(公告)号：WO2004038802A3

公开(公告)日：2004-09-10

申请号：PCT/DE0303354

申请日：2003-10-10

Applicant: INFINEON TECHNOLOGIES AG ,  BREDERLOW RALF ,  HARTWICH JESSICA ,  PACHA CHRISTIAN ,  ROESNER WOLFGANG ,  SCHULZ THOMAS

Inventor： BREDERLOW RALF ,  HARTWICH JESSICA ,  PACHA CHRISTIAN ,  ROESNER WOLFGANG ,  SCHULZ THOMAS

IPC: H01L21/8242 ,  H01L21/84 ,  H01L27/108 ,  H01L27/12

CPC classification number: H01L27/1085 ,  H01L21/84 ,  H01L27/10805 ,  H01L27/1203

Abstract: Disclosed is an integrated circuit arrangement (140), among others, comprising a preferably planar transistor (142) and a capacitor (144). The lower electrode of the capacitor (144) is disposed within an SOl substrate along with a channel section of the transistor (142). The inventive circuit arrangement (140) is easy to produce and has excellent electronic properties.

Abstract translation: 尤其公开了包含优选平面晶体管（142）和电容器（144）的集成电路装置（140）。 电容器（144）的下电极与SOI衬底中的晶体管（142）的沟道区共同布置。 电路装置（140）容易制造并具有优异的电子特性。

公开(公告)号：WO0106542A3

公开(公告)日：2001-07-19

申请号：PCT/DE0002316

申请日：2000-07-17

Applicant: INFINEON TECHNOLOGIES AG ,  SCHULZ THOMAS ,  ROESNER WOLFGANG ,  FRANOSCH MARTIN ,  SCHAEFER HERBERT ,  RISCH LOTHAR ,  AEUGLE THOMAS

Inventor： SCHULZ THOMAS ,  ROESNER WOLFGANG ,  FRANOSCH MARTIN ,  SCHAEFER HERBERT ,  RISCH LOTHAR ,  AEUGLE THOMAS

IPC: H01L21/335 ,  H01L21/336 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/76 ,  H01L51/00 ,  H01L51/05 ,  H01L51/30

CPC classification number: B82Y10/00 ,  H01L21/823487 ,  H01L27/088 ,  H01L29/66439 ,  H01L29/66666 ,  H01L29/7613 ,  H01L51/0048 ,  H01L51/0052 ,  H01L51/0512

Abstract: According to the invention, a double gate MOSFET semiconductor layer structure is formed on a substrate (1). This structure is comprised of a first and of a second gate electrode (10A, 10B) between which a semiconductor channel layer zone (4A) is embedded, and of a source region (2A) and a drain region (2B) which are arranged on opposite faces of the semiconductor channel layer zone (4A). At least one additional semiconductor channel layer zone (6A) is provided on one of the gate electrodes (10B). The faces of the at least one additional semiconductor channel layer zone are also contacted by the source region (2A) and drain region (2B).

Abstract translation: 在衬底（1）上构建双栅MOSFET半导体层结构。 这在半导体沟道层区的相对的端面由第一和在其之间的半导体沟道层区域（4A）被嵌入第二栅电极（10A，10B），以及源极（2A）和漏极区域（2b）中的 （4A）被布置。 在其中一个栅电极（10B）上提供至少一个另外的半导体沟道层区域（6A），其端面同样与源极（2A）和漏极区域（2B）接触。

公开(公告)号：WO2004040644A3

公开(公告)日：2004-08-12

申请号：PCT/DE0303589

申请日：2003-10-29

Applicant: INFINEON TECHNOLOGIES AG ,  GRAHAM ANDREW ,  HOFMANN FRANZ ,  HOENLEIN WOLFGANG ,  KRETZ JOHANNES ,  KREUPL FRANZ ,  LANDGRAF ERHARD ,  LUYKEN RICHARD JOHANNES ,  ROESNER WOLFGANG ,  SCHULZ THOMAS ,  SPECHT MICHAEL

Inventor： GRAHAM ANDREW ,  HOFMANN FRANZ ,  HOENLEIN WOLFGANG ,  KRETZ JOHANNES ,  KREUPL FRANZ ,  LANDGRAF ERHARD ,  LUYKEN RICHARD JOHANNES ,  ROESNER WOLFGANG ,  SCHULZ THOMAS ,  SPECHT MICHAEL

IPC: G11C13/02 ,  H01L21/8242 ,  H01L27/108 ,  H01L51/00 ,  H01L51/05 ,  H01L51/30 ,  H01L21/8239 ,  H01L51/20

CPC classification number: G11C13/025 ,  B82Y10/00 ,  G11C13/0033 ,  G11C2213/16 ,  H01L27/10841 ,  H01L27/10864 ,  H01L27/10876 ,  H01L27/283 ,  H01L51/0048 ,  H01L51/0052 ,  H01L51/0512 ,  H01L51/057

Abstract: The invention relates to a memory cell, memory cell arrangement, structuring arrangement and method for production of a memory cell. The memory cell has a vertical gate transistor and a memory capacitor, whereby the vertical gate transistor comprises a semiconducting nanostructure, grown on at least part of the memory capacitor.

Abstract translation: 本发明涉及一种存储器单元，存储器单元阵列，纹理化装置和一种用于制造存储器单元的方法。 该存储单元有一个垂直的开关晶体管和存储电容器，所述具有半导体纳米结构垂直开关晶体管上生长至少存储电容器的一部分。

公开(公告)号：WO2004038770A3

公开(公告)日：2004-09-23

申请号：PCT/DE0303355

申请日：2003-10-10

Applicant: INFINEON TECHNOLOGIES AG ,  BREDERLOW RALF ,  HARTWICH JESSICA ,  PACHA CHRISTIAN ,  ROESNER WOLFGANG ,  SCHULZ THOMAS

Inventor： BREDERLOW RALF ,  HARTWICH JESSICA ,  PACHA CHRISTIAN ,  ROESNER WOLFGANG ,  SCHULZ THOMAS

IPC: H01L21/336 ,  H01L21/8242 ,  H01L21/84 ,  H01L27/06 ,  H01L27/108 ,  H01L27/12 ,  H01L29/786 ,  H01L21/02

CPC classification number: H01L29/785 ,  H01L21/845 ,  H01L27/0629 ,  H01L27/108 ,  H01L27/10805 ,  H01L27/10823 ,  H01L27/10826 ,  H01L27/1085 ,  H01L27/10873 ,  H01L27/10876 ,  H01L27/10879 ,  H01L27/1211 ,  H01L27/13 ,  H01L28/60 ,  H01L29/66795

Abstract: Disclosed is an integrated circuit arrangement (120), among others, comprising a transistor (122), preferably a FinFET, and a capacitor (124). The lower electrode of the capacitor (124) is disposed within an SOl substrate along with a channel section of the transistor (122). The inventive circuit arrangement (120) is easy to produce and has excellent electronic properties.

Abstract translation: 进行了说明，除其他外，集成电路装置（120）包括一个晶体管（122），优选地为所谓的FinFET，和电容器（124）。 电容器（124）的下部电极与在SOI衬底的晶体管（122）的沟道区布置在一起。 所述的电路装置（120）是容易制造并具有优良的电子特性。