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公开(公告)号：WO2004097838A3
公开(公告)日：2005-02-24
申请号：PCT/EP2004050322
申请日：2004-03-17
Applicant: INFINEON TECHNOLOGIES AG , GRUBER WOLFGANG , KAKOSCHKE RONALD , SCHWEIZER THOMAS , WEGERTSEDER DOMINIK
Inventor： GRUBER WOLFGANG , KAKOSCHKE RONALD , SCHWEIZER THOMAS , WEGERTSEDER DOMINIK
IPC: G11C5/02 , H01L25/18 , H01L23/538
CPC classification number: G11C5/025 , H01L25/18 , H01L2924/0002 , H01L2924/00
Abstract: The invention relates to a memory-circuit arrangement (10) wherein parts of the memory are located on two different substrates. A memory cell field (16), amongst other things, is located on one substrate. A control switch (38), amongst other things, is located on the other substrate. The production costs thereof are significantly reduced due to the clever division of memory.
Abstract translation: 中描述了一种存储电路装置（10），其中，所述存储器的所述部分位于两个不同的衬底。 是，除其他外，在一个衬底上的存储单元阵列（16）。 是，除其他外，在另一方的基板上的控制电路（38）。 存储器的巧妙划分，在生产费用可以显著降低。
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公开(公告)号：WO2004080031A3
公开(公告)日：2005-05-06
申请号：PCT/DE2004000407
申请日：2004-03-03
Applicant: INFINEON TECHNOLOGIES AG , HEWEL KARL-HARALD , ROTH MANFRED , RUEPING STEFAN , SCHWEIZER THOMAS , SEIFERT JEAN-PIERRE , WEGERTSEDER DOMINIK
Inventor： HEWEL KARL-HARALD , ROTH MANFRED , RUEPING STEFAN , SCHWEIZER THOMAS , SEIFERT JEAN-PIERRE , WEGERTSEDER DOMINIK
Abstract: The invention relates to an interface arrangement (1) for exchanging data between a number of devices (3A, 3B) that has a freely configurable circuit logic (1A, 1B), which can be configured by the devices (3A, 3b) and once completely configured, enables a data exchange between the devices (3A, 3B) via the interface arrangement (1).
Abstract translation: 接口装置（1）进行数据的多个装置（3A，3B），其包括一个可配置的逻辑电路之间的交换（1A，1B）的装置（3A，3B）是可配置的和设备之间的数据交换的完整的配置后（3A ，3B）（经由接口设备）成为可能。
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公开(公告)号：DE10309312B4
公开(公告)日：2006-01-26
申请号：DE10309312
申请日：2003-03-04
Applicant: INFINEON TECHNOLOGIES AG
Inventor： WEGERTSEDER DOMINIK , SEIFERT JEAN-PIERRE , RUEPING STEFAN , HEWEL HARALD , ROTH MANFRED , SCHWEIZER THOMAS
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公开(公告)号：DE10350869A1
公开(公告)日：2005-06-09
申请号：DE10350869
申请日：2003-10-31
Applicant: INFINEON TECHNOLOGIES AG
Inventor： SCHWEIZER THOMAS , JANKE MARCUS
Abstract: The garment has a sensor (S) for determining movement of an athlete body. Actuator (A) and/or indicator (D) convey a message in the form of optical or acoustic or tactile sensory signals to the athlete when the body movement sensed by the sensor exceeds a certain limit, for correcting the body posture. The sensor, actuator, and indicator connected by thin conductor threads are inserted in the canvas of the garment. The sensor is connected to an integrated circuit (IC) that is connected to a memory (M), which stores the sensor signals for future retroactive analysis.
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公开(公告)号：DE10338029A1
公开(公告)日：2005-04-07
申请号：DE10338029
申请日：2003-08-19
Applicant: INFINEON TECHNOLOGIES AG
Inventor： JANKE MARCUS , SCHWEIZER THOMAS
Abstract: The fabric (9) with two sets (3, 4) of electrically conductive threads and an insulating material is provided with a unit for monitoring the electrical state of the fabric. An independent claim is also included for an item of clothing which is made at least in parts of the proposed fabric.
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Patent Agency Ranking
公开(公告)号：DE10309313B4
公开(公告)日：2006-03-09
申请号：DE10309313
申请日：2003-03-04
Applicant: INFINEON TECHNOLOGIES AG
Inventor： WEGERTSEDER DOMINIK , RUEPING STEFAN , SCHWEIZER THOMAS , ROTH MANFRED , HEWEL HARALD , SEIFERT JEAN-PIERRE
IPC: G01R31/3185 , G06F11/20 , G06K19/073
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公开(公告)号：DE10319271A1
公开(公告)日：2004-11-25
申请号：DE10319271
申请日：2003-04-29
Applicant: INFINEON TECHNOLOGIES AG
Inventor： GRUBER WOLFGANG , KAKOSCHKE RONALD , SCHWEIZER THOMAS , WEGERTSEDER DOMINIK
IPC: G11C5/02 , H01L25/18 , H01L25/065 , G11C11/34
Abstract: A memory circuit arrangement and fabrication method thereof are presented in which the parts of the memory circuit arrangement are situated on two different substrates. An integrated memory cell array is situated on one substrate. An integrated control circuit that controls access to the memory cells is situated on the other (logic circuit) substrate. The control circuit controls sequences when reading, writing or erasing content of a memory cell. The logic circuit substrate also contains a CPU and encryption coprocessor. The memory circuit contains a sense amplifier, with the aid of which the memory state of a memory cell can be determined, and a decoding circuit that selects a word or bit line.
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公开(公告)号：DE10309312A1
公开(公告)日：2004-09-23
申请号：DE10309312
申请日：2003-03-04
Applicant: INFINEON TECHNOLOGIES AG
Inventor： WEGERTSEDER DOMINIK , SEIFERT JEAN-PIERRE , RUEPING STEFAN , HEWEL HARALD , ROTH MANFRED , SCHWEIZER THOMAS
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公开(公告)号：DE502004008318D1
公开(公告)日：2008-12-04
申请号：DE502004008318
申请日：2004-03-17
Applicant: INFINEON TECHNOLOGIES AG
Inventor： GRUBER WOLFGANG , KAKOSCHKE RONALD , SCHWEIZER THOMAS , WEGERTSEDER DOMINIK
IPC: G11C5/02 , H01L23/538 , H01L25/18
Abstract: A memory circuit arrangement and fabrication method thereof are presented in which the parts of the memory circuit arrangement are situated on two different substrates. An integrated memory cell array is situated on one substrate. An integrated control circuit that controls access to the memory cells is situated on the other (logic circuit) substrate. The control circuit controls sequences when reading, writing or erasing content of a memory cell. The logic circuit substrate also contains a CPU and encryption coprocessor. The memory circuit contains a sense amplifier, with the aid of which the memory state of a memory cell can be determined, and a decoding circuit that selects a word or bit line.
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公开(公告)号：DE10310535A1
公开(公告)日：2004-09-30
申请号：DE10310535
申请日：2003-03-11
Applicant: INFINEON TECHNOLOGIES AG
Inventor： WEGERTSEDER DOMINIK , RUEPING STEFAN , HEWEL HARALD , SCHWEIZER THOMAS , SEIFERT JEAN-PIERRE , ROTH MANFRED
Abstract: Microprocessor card (2), e.g. a chip card, has a microcontroller (1) with a predefined functional scope and a configuration module (3) that is connected to the controller. The configuration module is a field-programmable gate array and is integrated in the controller.
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