公开(公告)号：DE59310168D1

公开(公告)日：2001-06-07

申请号：DE59310168

申请日：1993-02-19

Applicant: INFINEON TECHNOLOGIES AG

Inventor： SAVIGNAC DOMINIQUE DR ,  SOMMER DIPL-PHYS ,  WEIDENHOEFER DIPL-ING

IPC: G11C11/413 ,  G11C11/401 ,  G11C29/00 ,  G11C29/04 ,  G11C5/00 ,  G06F11/20

Abstract: The column redundancy device for a memory has a memory blocks (BK1... N), with memory cells arranged in x rows and y columns, redundant memory cells, which are arranged in b rows and c columns, a column decoder (CDEC) with c redundant column decoders (RCD1 ... N), and d coding elements (CF1,1 ... CFP,4). Each column decoder (RCD1 ... 4) is assigned to one of the c redundant columns of each memory block (BK1 ... N). Each of the d coding elements (CF1,1 ... CFP,4) includes means of decoding addresses, and can thus be assigned to any memory block (BK1... N).