公开(公告)号：JP2000252440A

公开(公告)日：2000-09-14

申请号：JP2000046287

申请日：2000-02-23

Applicant: INFINEON TECHNOLOGIES AG

Inventor： FEURLE ROBERT ,  MANDEL SABINE ,  SAVIGNAC DOMINIQUE DR ,  SCHNEIDER HELMUT

IPC: G11C7/18 ,  H01L21/8242 ,  H01L23/522 ,  H01L27/108

Abstract: PROBLEM TO BE SOLVED: To avoid the affect of unevenness of the element at edge part on a crossover region or twist region of a bit line by providing with a bit line comprising no bit line twist part with a dummy contact communicated with another plane. SOLUTION: Bit lines BL1, BL2; BL5, BL6; BL9, BL10 comprise a bit line twist part. Bit lines BL3, BL4, BL7, and BL8 comprise no bit line twist part. In order to avoid a proximity effect caused by discontinuity or unevenness in a region near the word lines, even the bit lines BL3, BL4, BL7, and BL8 comprising no crossover or twist part are provided with dummy contacts 8-11. The dummy contacts 8-11 are connected to a word line plane from upward from a bit line plane, and terminate there. Thus, the effect of unevenness of word line is avoided.

公开(公告)号：JP2001203172A

公开(公告)日：2001-07-27

申请号：JP2000383537

申请日：2000-12-18

Applicant: INFINEON TECHNOLOGIES AG

Inventor： FEURLE ROBERT ,  SAVIGNAC DOMINIQUE DR

IPC: H01L21/301 ,  H01L23/31

Abstract: PROBLEM TO BE SOLVED: To enable simply avoiding cracks with high reliability when a semiconductor wafer is cut off, by improving equipment for cutting off semiconductor elements from a semiconductor wafer along a scribe line. SOLUTION: In this equipment for cutting off semiconductor elements, an insulating layer is formed on a semiconductor wafer, a plurality of metallization surfaces are formed on the insulating layer, and the uppermost metallization surface from among these metallization surfaces is connected electrically with the metallization surface below the uppermost metallization surface via a connection layer with a connection hole. An additional recessed part, which is formed together with the connection hole is formed on the insulating layer at an interim region between the semiconductor elements and the scribe line, so that the insulating layer is thinned.

公开(公告)号：DE50115046D1

公开(公告)日：2009-10-01

申请号：DE50115046

申请日：2001-08-21

Applicant: INFINEON TECHNOLOGIES AG

Inventor： FEURLE ROBERT ,  SAVIGNAC DOMINIQUE DR

IPC: G11C11/401 ,  H01L27/108 ,  G11C11/34 ,  G11C11/407 ,  H01L21/334 ,  H01L21/8242 ,  H01L27/06

Abstract: An integrated store, has storage cells which each comprise a selection transistor and a storage capacitance with each storage cell, the storage capacitance is connected via the selection transistor to one of several column lines (BLK). With each storage cell, a control terminal of the selection transistor is connected to one of several row-lines (WLN) and with the buffer capacitances in each case one contact (K2) is connected to a further one of the column lines (BLK) and the buffer capacitances (CP) are arranged in such a way that the connections (GB) between the respective buffer capacitance and the contact (K2) is arranged parallel to another one of the row-lines (WLK).

公开(公告)号：DE59310168D1

公开(公告)日：2001-06-07

申请号：DE59310168

申请日：1993-02-19

Applicant: INFINEON TECHNOLOGIES AG

Inventor： SAVIGNAC DOMINIQUE DR ,  SOMMER DIPL-PHYS ,  WEIDENHOEFER DIPL-ING

IPC: G11C11/413 ,  G11C11/401 ,  G11C29/00 ,  G11C29/04 ,  G11C5/00 ,  G06F11/20

Abstract: The column redundancy device for a memory has a memory blocks (BK1... N), with memory cells arranged in x rows and y columns, redundant memory cells, which are arranged in b rows and c columns, a column decoder (CDEC) with c redundant column decoders (RCD1 ... N), and d coding elements (CF1,1 ... CFP,4). Each column decoder (RCD1 ... 4) is assigned to one of the c redundant columns of each memory block (BK1 ... N). Each of the d coding elements (CF1,1 ... CFP,4) includes means of decoding addresses, and can thus be assigned to any memory block (BK1... N).

公开(公告)号：AT200939T

公开(公告)日：2001-05-15

申请号：AT93102667

申请日：1993-02-19

Applicant: INFINEON TECHNOLOGIES AG

Inventor： SAVIGNAC DOMINIQUE DR ,  SOMMER DIETHER DIPL-PHYS ,  WEIDENHOEFER JUERGEN DIPL-ING

IPC: G11C11/413 ,  G11C11/401 ,  G11C29/00 ,  G11C29/04 ,  G11C5/00 ,  G06F11/20

Abstract: The column redundancy device for a memory has a memory blocks (BK1... N), with memory cells arranged in x rows and y columns, redundant memory cells, which are arranged in b rows and c columns, a column decoder (CDEC) with c redundant column decoders (RCD1 ... N), and d coding elements (CF1,1 ... CFP,4). Each column decoder (RCD1 ... 4) is assigned to one of the c redundant columns of each memory block (BK1 ... N). Each of the d coding elements (CF1,1 ... CFP,4) includes means of decoding addresses, and can thus be assigned to any memory block (BK1... N).