公开(公告)号：DE102004031112A1

公开(公告)日：2006-01-19

申请号：DE102004031112

申请日：2004-06-28

Applicant: INFINEON TECHNOLOGIES AG

Inventor： THALMANN ERWIN ,  BOLDT SVEN

IPC: H01L23/525 ,  H01L23/58 ,  H01L27/08

Abstract: An electronic circuit for adjusting the potential difference (102) between a node point (101) and a reference node (103) comprises series switches (106a-n) between the nodes and a connection to apply a control potential (105c) to give an adjustable voltage drop (107a-n). A separation device (108) is in series with the switches. An independent claim is also included for an adjusting process for the above circuit.

公开(公告)号：DE102004028989A1

公开(公告)日：2006-01-12

申请号：DE102004028989

申请日：2004-06-16

Applicant: INFINEON TECHNOLOGIES AG

Inventor： THALMANN ERWIN ,  BOLDT SVEN

IPC: G01C5/06 ,  G11C5/04 ,  H01L25/065 ,  H05K1/14 ,  H05K1/18 ,  H05K7/20

Abstract: The invention provides an electronic circuit apparatus having a plurality of electronic circuit units ( 101 a- 101 n), a circuit board ( 102 ) and a connection unit ( 103 ), the circuit board ( 102 ) having a basic board element ( 200 ) and a plurality of additional board elements ( 201 - 204 ), the plurality of additional board elements ( 201 - 204 ) being connected to the basic board element ( 200 ) by means of connecting elements ( 301 - 304 ) and the circuit units being arranged on the additional board elements ( 201 - 204 ) in such a way that in each case identical signal propagation times are provided between the circuit units arranged on an additional board ( 201 - 204 ) and the connection unit ( 103 ).

公开(公告)号：DE102004020546A1

公开(公告)日：2005-11-24

申请号：DE102004020546

申请日：2004-04-27

Applicant: INFINEON TECHNOLOGIES AG

Inventor： THALMANN ERWIN ,  BOLDT SVEN

IPC: G11C8/00 ,  G11C29/00

Abstract: Electronic memory apparatus, and method for deactivating redundant bit lines or word lines An electronic memory apparatus ( 100 ) having a memory cell array ( 101 ), a column address decoding unit ( 102 ) for decoding a column addressing signal ( 105 ) and for actuating an addressed bit line in the memory cell array ( 101 ), a column redundancy activation unit ( 103 ) for activating a redundant bit line when a currently used bit line has been determined to be faulty during testing of the memory apparatus ( 100 ), a row address decoding unit ( 202 ) for decoding a row addressing signal ( 205 ) and for actuating an addressed word line in the memory cell array ( 101 ), and a row redundancy activation unit ( 203 ) for activating a redundant word line when a currently used word line has been determined to be faulty during testing of the memory apparatus ( 100 ). A column deactivation unit deactivates unused, redundant bit lines and those bit lines which have been determined to be faulty during testing of the memory apparatus, and a row deactivation unit ( 204 ) deactivates unused, redundant word lines and those word lines which have been determined to be faulty during testing of the memory apparatus ( 100 ).

公开(公告)号：DE102004001653B3

公开(公告)日：2005-11-03

申请号：DE102004001653

申请日：2004-01-12

Applicant: INFINEON TECHNOLOGIES AG

Inventor： THALMANN ERWIN

IPC: G01R31/3183 ,  G11C8/00 ,  G11C29/00 ,  G11C29/56

Abstract: The invention provides a test apparatus for testing a circuit unit to be tested. In one embodiment, a circuit unit incorporating aspects of the invention includes a data memory bank ( 106 ) for storing test mode data which are fed via an address control terminal ( 201 ) and with which the circuit unit ( 101 ) to be tested can be tested, provision being made of at least one test mode bank ( 104 a- 104 n) for providing at least one test mode data set ( 204 a- 204 n) and at least one activation signal ( 205 a- 205 n), at least one register bank ( 103 a- 103 n) and a transfer device for transferring a test mode data set ( 204 a- 204 n) from a register bank ( 103 a- 103 n) to the data memory bank ( 106 ) in a manner dependent on the activation signal ( 205 a- 205 n).

公开(公告)号：DE10345980A1

公开(公告)日：2005-05-12

申请号：DE10345980

申请日：2003-10-02

Applicant: INFINEON TECHNOLOGIES AG

Inventor： THALMANN ERWIN

IPC: G11C29/00 ,  G11C29/56

Abstract: Memory module (101) testing appliance contains test system (100) for providing test data (206) and analysing test result data (207), as well as data bus (111), write-read channel (104), control bus (105) and address bus (109), all with specified functions.There is also included coupling module (200) between test system and tested memory module for connecting number of tester individual data lines of tester channel (110) to number of memory module individual data lines of data bus.

公开(公告)号：DE10338677B3

公开(公告)日：2005-04-21

申请号：DE10338677

申请日：2003-08-22

Applicant: INFINEON TECHNOLOGIES AG

Inventor： THALMANN ERWIN ,  MOSER MANFRED

IPC: G01R31/02 ,  G01R31/3183 ,  G01R31/319 ,  G11C29/00 ,  G11C29/56

Abstract: The invention provides a test apparatus for testing a circuit unit (113) to be tested which has a data input unit (104) for supplying a nominal data signal (117) to the circuit unit (113) to be tested, and a driver unit (108) for driving the actual data signal (105) (which is emitted from the circuit unit (113) to be tested as a function of the nominal data signal (117) supplied to it) to a data output unit (109) with at least one further signal, by means of which the serviceability of the circuit unit (113) to be tested can be determined being diverted to the data output unit (109).

公开(公告)号：DE10338678B4

公开(公告)日：2006-04-20

申请号：DE10338678

申请日：2003-08-22

Applicant: INFINEON TECHNOLOGIES AG

Inventor： THALMANN ERWIN

IPC: G01R31/3183 ,  G01R31/317 ,  G01R31/319 ,  G01R31/3193 ,  G06F11/00 ,  G11C29/00

Abstract: Apparatus and Method for Testing Circuit Units To Be Tested. According to one aspect, a test apparatus for testing circuit units to be tested, includes a nominal data production unit for production of a nominal data stream, a comparison device for comparison of an actual data stream which is emitted from the circuit unit to be tested as a function of the nominal data stream that is supplied with the nominal data stream; and a compression device for compression of an intermediate result signal which is emitted from the comparison device as a function of the comparison into a test result signal, with the intermediate result signal ( 108 ) which is emitted from the comparison device being temporarily stored in a buffer storage device with the intermediate result signal which is temporarily stored in a buffer storage device being read by means of a read unit.

公开(公告)号：DE102004027854A1

公开(公告)日：2006-01-19

申请号：DE102004027854

申请日：2004-06-08

Applicant: INFINEON TECHNOLOGIES AG

Inventor： THALMANN ERWIN ,  MOSER MANFRED ,  MYSLIWITZ DANIEL

IPC: G01R31/12 ,  G01R31/317 ,  G01R31/3183 ,  G01R31/319 ,  G11C29/00

Abstract: The invention provides a test apparatus for testing a circuit unit ( 101 ) to be tested having a test system ( 100 ), a control bus ( 102 ) for transferring control data ( 106 ), an address bus ( 103 ) for transferring addressing data ( 107 ) and a data bus ( 104 ) for exchanging test data ( 108 ) between the test system ( 100 ) and the circuit unit ( 101 ) to be tested. A voltage generating device ( 200 ) connected between the test system ( 100 ) and the circuit unit ( 101 ) to be tested serves for generating a predeterminable operating voltage output signal ( 202, 202 a- 202 n) for the voltage supply of the circuit unit ( 101 ) to be tested in a manner dependent on a control signal ( 211 ) that is provided by the test system ( 100 ) and fed via the control bus ( 102 ).

公开(公告)号：DE102004025702A1

公开(公告)日：2005-12-22

申请号：DE102004025702

申请日：2004-05-26

Applicant: INFINEON TECHNOLOGIES AG

Inventor： THALMANN ERWIN

IPC: G11C7/10 ,  G11C11/4096

Abstract: The electronic circuit units [109] may be configured in various ways. This is achieved by applying a control signal [106] and a device address [103]. The inputs are received by a circuit [100] that determines the operational configuration of the electronic circuits. The circuits may be memories with x4,x8,x16 etc configurations.

公开(公告)号：DE10338678A1

公开(公告)日：2005-03-31

申请号：DE10338678

申请日：2003-08-22

Applicant: INFINEON TECHNOLOGIES AG

Inventor： THALMANN ERWIN

IPC: G01R31/317 ,  G01R31/3183 ,  G01R31/319 ,  G01R31/3193 ,  G06F11/00 ,  G11C29/00

Abstract: Apparatus and Method for Testing Circuit Units To Be Tested. According to one aspect, a test apparatus for testing circuit units to be tested, includes a nominal data production unit for production of a nominal data stream, a comparison device for comparison of an actual data stream which is emitted from the circuit unit to be tested as a function of the nominal data stream that is supplied with the nominal data stream; and a compression device for compression of an intermediate result signal which is emitted from the comparison device as a function of the comparison into a test result signal, with the intermediate result signal ( 108 ) which is emitted from the comparison device being temporarily stored in a buffer storage device with the intermediate result signal which is temporarily stored in a buffer storage device being read by means of a read unit.