公开(公告)号：DE102004027854A1

公开(公告)日：2006-01-19

申请号：DE102004027854

申请日：2004-06-08

Applicant: INFINEON TECHNOLOGIES AG

Inventor： THALMANN ERWIN ,  MOSER MANFRED ,  MYSLIWITZ DANIEL

IPC: G01R31/12 ,  G01R31/317 ,  G01R31/3183 ,  G01R31/319 ,  G11C29/00

Abstract: The invention provides a test apparatus for testing a circuit unit ( 101 ) to be tested having a test system ( 100 ), a control bus ( 102 ) for transferring control data ( 106 ), an address bus ( 103 ) for transferring addressing data ( 107 ) and a data bus ( 104 ) for exchanging test data ( 108 ) between the test system ( 100 ) and the circuit unit ( 101 ) to be tested. A voltage generating device ( 200 ) connected between the test system ( 100 ) and the circuit unit ( 101 ) to be tested serves for generating a predeterminable operating voltage output signal ( 202, 202 a- 202 n) for the voltage supply of the circuit unit ( 101 ) to be tested in a manner dependent on a control signal ( 211 ) that is provided by the test system ( 100 ) and fed via the control bus ( 102 ).

公开(公告)号：DE10237121A1

公开(公告)日：2004-03-04

申请号：DE10237121

申请日：2002-08-13

Applicant: INFINEON TECHNOLOGIES AG

Inventor： VERSEN MARTIN ,  MOSER MANFRED ,  TILCH MARTIN ,  NAIR SREDNESH

IPC: G06F12/16 ,  H04L1/22

Abstract: A memory management configuration and a method for the memory management of a main memory are provided. An access to a memory area of the main memory that is known to be defective is diverted into an additional memory.

公开(公告)号：DE10203570A1

公开(公告)日：2003-08-14

申请号：DE10203570

申请日：2002-01-30

Applicant: INFINEON TECHNOLOGIES AG

Inventor： ADLER FRANK ,  MOSER MANFRED ,  HUBER THOMAS

IPC: G11C29/02 ,  G11C29/00

Abstract: The method involves making read and write accesses to the semiconducting component by writing a first information item by driving a memory address so no address lines (L1-6) are electrically biased, writing a different second item, whereby a second address is selected so that only one address line is biased, reading the first memory address, which is driven so no address lines are biased, and checking which information item was read out.

公开(公告)号：DE10111711A1

公开(公告)日：2002-09-26

申请号：DE10111711

申请日：2001-03-12

Applicant: INFINEON TECHNOLOGIES AG

Inventor： ANGENENDT GUIDO ,  MOSER MANFRED ,  SCHRAMM ACHIM

IPC: G11C29/00

Abstract: The method involves fault detection logic (20) in the memory detecting faults and detecting faulty rows and/or columns in a memory cell field in the event of a fault. The memory has replacement rows and/or columns (32,34) and the fault detection logic permanently replaces the faulty rows and/or columns with the replacement rows and/or columns. Independent claims are also included for the following an arrangement for repairing a memory and fault monitoring logic.

公开(公告)号：DE102004059671A1

公开(公告)日：2006-06-14

申请号：DE102004059671

申请日：2004-12-10

Applicant: INFINEON TECHNOLOGIES AG

Inventor： ANTRETTER RICHARD ,  MOSER MANFRED

IPC: G11C11/406

公开(公告)号：DE10345978A1

公开(公告)日：2005-04-28

申请号：DE10345978

申请日：2003-10-02

Applicant: INFINEON TECHNOLOGIES AG

Inventor： THALMANN ERWIN ,  BOLDT SVEN ,  MOSER MANFRED

IPC: G06F3/06 ,  G06F11/00 ,  G06F11/07 ,  G06F11/20 ,  G06F12/00 ,  G06F12/06

Abstract: The device includes a memory module with a memory bank (101a), and at least one further memory bank (101b-101n) which is activated by bank select signals (205a-205l) provided by a controller-processor unit, and supplied via a control bus (104). The controller-processor unit preferably has a test mode unit (200), which outputs a logical combination signal to determine the logical combination of the bank select signal. An independent claim is included for a data storage method.

公开(公告)号：DE10140757A1

公开(公告)日：2003-03-13

申请号：DE10140757

申请日：2001-08-20

Applicant: INFINEON TECHNOLOGIES AG

Inventor： ADLER FRANK ,  VERSEN MARTIN ,  MOSER MANFRED ,  HUBER THOMAS

IPC: G01R31/28 ,  G01R31/30 ,  G11C29/02 ,  G11C29/50

Abstract: Signal transit times on printed circuit boards which are equipped with all the passive components but without any active components can be determined using automatic standard test equipment composed of a standard test unit and a performance board with fittings attached thereto. In that first, using a standard routine of the test unit, a transit time is measured on the performance board from the CIF connector as far as the fitting, then a printed circuit board is plugged into the fitting location determined for it and then the sum transit time of the CIF connector is measured as far as the landing pad on the printed circuit board. By forming differences between the two measured values, the transit times on a printed circuit board can be measured with a high degree of precision with the automatic standard test equipment used in standard module testing technology.

公开(公告)号：DE102004025893A1

公开(公告)日：2005-12-22

申请号：DE102004025893

申请日：2004-05-27

Applicant: INFINEON TECHNOLOGIES AG

Inventor： BOLDT SVEN ,  THALMANN ERWIN ,  MOSER MANFRED ,  NEYER THOMAS

IPC: G11C7/00 ,  G11C29/00 ,  G11C29/24

Abstract: The invention provides a test apparatus for testing an electronic circuit device ( 101 ) to be tested by means of a test system ( 100 ), having an interface unit ( 102 ) for connecting the circuit device ( 101 ) to be tested to the test system ( 100 ), an address decoding unit ( 107 ) for decoding external addressing data ( 104 ) input by means of the test system ( 100 ) into internal addressing data ( 110, 112 ) and for addressing memory cells of a memory cell array ( 108 ) of the circuit device ( 101 ) to be tested with the internal addressing data ( 110, 112 ), and a memory data converter ( 115 ) for converting logical memory data ( 106 ), which are fed by the test system ( 100 ), into physical memory data ( 114 ). The memory data converter ( 115 ) carries out a conversion of the logical memory data ( 106 ) fed by the test system ( 100 ) into physical memory data ( 114 ) in a manner dependent on the internal addressing data ( 110, 112 ) of the circuit device ( 101 ) to be tested.

公开(公告)号：DE10329646A1

公开(公告)日：2004-09-16

申请号：DE10329646

申请日：2003-07-01

Applicant: INFINEON TECHNOLOGIES AG

Inventor： PERNER MARTIN ,  MOSER MANFRED

IPC: H01L23/525 ,  H01L25/065 ,  H01L23/58

Abstract: The component (11) includes several identical, parallel-connected integrated circuits, typically memory chips (1,2). Each chip contains two terminal contacts (CS1,2) for supply of two selection signals.There are selection contacts (12,22), via which selection signals are supplied to component. Selection logic (3) can switch-off each one of two memory chips. Preferably switch-off capability is carried out by so-called E-fuse. Of several functional chips, several can be switched off. Independent claims are included for method for operating electronic component during testing.

公开(公告)号：DE10338677B3

公开(公告)日：2005-04-21

申请号：DE10338677

申请日：2003-08-22

Applicant: INFINEON TECHNOLOGIES AG

Inventor： THALMANN ERWIN ,  MOSER MANFRED

IPC: G01R31/02 ,  G01R31/3183 ,  G01R31/319 ,  G11C29/00 ,  G11C29/56

Abstract: The invention provides a test apparatus for testing a circuit unit (113) to be tested which has a data input unit (104) for supplying a nominal data signal (117) to the circuit unit (113) to be tested, and a driver unit (108) for driving the actual data signal (105) (which is emitted from the circuit unit (113) to be tested as a function of the nominal data signal (117) supplied to it) to a data output unit (109) with at least one further signal, by means of which the serviceability of the circuit unit (113) to be tested can be determined being diverted to the data output unit (109).