公开(公告)号：JP2003296200A

公开(公告)日：2003-10-17

申请号：JP2003074641

申请日：2003-03-18

Applicant: Infineon Technologies Ag ,  インフィネオン テクノロジーズ アクチェンゲゼルシャフト

Inventor： ADLER FRANK ,  FOERSTE MARKUS ,  THIELE FRANK

IPC: G06F12/16 ,  G01R31/26 ,  G11C29/56 ,  H01L21/66

CPC classification number: G11C29/56 ,  G11C2029/1208 ,  G11C2029/5604 ,  G11C2029/5606

Abstract: PROBLEM TO BE SOLVED: To provide a method capable of surely and comprehensively testing memory modules on a computer system. SOLUTION: This method comprises processes of a) connecting memory modules to the computer system; b) reading a configuration file; c) inputting identifiers of the connected memory modules to the computer system; d) comparing the number of connected memory modules to the inputted number of memory module identifiers; e) reading test information for memory modules; f) testing the memory modules; g) storing the test result in a result file; h) evaluating the test result; and i) storing error information in a static file when a memory module has an error followed by outputting and further identifying the memory module having the error. COPYRIGHT: (C)2004,JPO

Abstract translation: 要解决的问题：提供一种能够可靠和全面地测试计算机系统上的存储器模块的方法。 解决方案：该方法包括以下过程：a）将存储器模块连接到计算机系统; b）读取配置文件; c）将连接的存储器模块的标识符输入到计算机系统; d）将连接的存储器模块的数量与输入的存储器模块标识符数量进行比较; e）读取内存模块的测试信息; f）测试内存模块; g）将测试结果存储在结果文件中; h）评估测试结果; 以及i）当存储器模块具有错误后输出并进一步识别具有该错误的存储器模块时，将错误信息存储在静态文件中。 版权所有（C）2004，JPO

公开(公告)号：DE10135582C1

公开(公告)日：2003-01-16

申请号：DE10135582

申请日：2001-07-20

Applicant: INFINEON TECHNOLOGIES AG

Inventor： THIELE FRANK

IPC: G01R31/317 ,  G11C7/10 ,  H03K5/00 ,  H03L7/081 ,  H03K5/135

Abstract: The IC has an adjustment circuit (3) provided with an equalization device (6) for synchronizing the internal clock signal (Ti) with delivered data, the equalization device supplied with setting data stored in a read-only memory (9) and setting data stored in a read/write memory (10), used respectively for initial and fine adjustment of the internal clock signal. An Independent claim for a method for adjusting an internal clock signal for an IC is also included.

公开(公告)号：DE10138883B4

公开(公告)日：2006-03-30

申请号：DE10138883

申请日：2001-08-08

Applicant: INFINEON TECHNOLOGIES AG

Inventor： RUCKERBAUER HERMANN ,  THIELE FRANK ,  KUHN JUSTUS

IPC: G06F13/14 ,  G06F1/12 ,  G06F13/16

Abstract: An internal clock signal of a logic/memory component that receives signals is transmitted as a reference clock to a transmitting logic/memory component. With the aid of the reference clock, the transmission clock of the output unit of the transmitting logic/memory component is generated, such that transmitted signals arrive in a receiving unit of the receiving component synchronously with the internal clock signal of that component.

公开(公告)号：DE10110627A1

公开(公告)日：2002-09-19

申请号：DE10110627

申请日：2001-03-06

Applicant: INFINEON TECHNOLOGIES AG

Inventor： THIELE FRANK

IPC: G11C29/46 ,  G11C29/00

Abstract: A memory controller (20) reads-in data sequences, via an interface (2), into a configuration register (4) of the RDRAM component (1). A data frequenncy, determining the RDRAM test function, is read-in into a free memory section (6) of the configuration register.The input data frequency, or its parts, are transmitted into a test option register (7) via a llink (6b). The test option register controls the selected test functions of the RDRAM in accordance with data frequency. Independent claims are included for the control executing circuit.

公开(公告)号：DE10213009A1

公开(公告)日：2003-10-09

申请号：DE10213009

申请日：2002-03-22

Applicant: INFINEON TECHNOLOGIES AG

Inventor： ADLER FRANK ,  THIELE FRANK ,  FOERSTE MARKUS

IPC: G06F12/16 ,  G01R31/26 ,  G11C29/56 ,  H01L21/66 ,  G11C29/00

Abstract: A method for electronically testing at least one memory module involves initially connecting the module to be tested to the computer system, electronically reading-in computer system configuration data, and then inputting a memory-module identifier for each memory module connected to the computer. An electronic comparison is made between the number of modules connected to the computer system and the number of memory module identifiers. Test information for the module being tested is then read in, followed by electronic testing of the module and the test results are automatically evaluated. If at least one module is faulty the erroneous data is electronically stored in at least one statistics data file. An Independent claim is given for a computer program product, as well as a computer program, for carrying out the electronic testing procedure.

公开(公告)号：DE10138883A1

公开(公告)日：2003-03-06

申请号：DE10138883

申请日：2001-08-08

Applicant: INFINEON TECHNOLOGIES AG

Inventor： RUCKERBAUER HERMANN ,  THIELE FRANK ,  KUHN JUSTUS

IPC: G06F1/12 ,  G06F13/14 ,  G06F13/16

Abstract: An internal clock signal of a logic/memory component that receives signals is transmitted as a reference clock to a transmitting logic/memory component. With the aid of the reference clock, the transmission clock of the output unit of the transmitting logic/memory component is generated, such that transmitted signals arrive in a receiving unit of the receiving component synchronously with the internal clock signal of that component.