公开(公告)号：JP2003296200A

公开(公告)日：2003-10-17

申请号：JP2003074641

申请日：2003-03-18

Applicant: Infineon Technologies Ag ,  インフィネオン テクノロジーズ アクチェンゲゼルシャフト

Inventor： ADLER FRANK ,  FOERSTE MARKUS ,  THIELE FRANK

IPC: G06F12/16 ,  G01R31/26 ,  G11C29/56 ,  H01L21/66

CPC classification number: G11C29/56 ,  G11C2029/1208 ,  G11C2029/5604 ,  G11C2029/5606

Abstract: PROBLEM TO BE SOLVED: To provide a method capable of surely and comprehensively testing memory modules on a computer system. SOLUTION: This method comprises processes of a) connecting memory modules to the computer system; b) reading a configuration file; c) inputting identifiers of the connected memory modules to the computer system; d) comparing the number of connected memory modules to the inputted number of memory module identifiers; e) reading test information for memory modules; f) testing the memory modules; g) storing the test result in a result file; h) evaluating the test result; and i) storing error information in a static file when a memory module has an error followed by outputting and further identifying the memory module having the error. COPYRIGHT: (C)2004,JPO

Abstract translation: 要解决的问题：提供一种能够可靠和全面地测试计算机系统上的存储器模块的方法。 解决方案：该方法包括以下过程：a）将存储器模块连接到计算机系统; b）读取配置文件; c）将连接的存储器模块的标识符输入到计算机系统; d）将连接的存储器模块的数量与输入的存储器模块标识符数量进行比较; e）读取内存模块的测试信息; f）测试内存模块; g）将测试结果存储在结果文件中; h）评估测试结果; 以及i）当存储器模块具有错误后输出并进一步识别具有该错误的存储器模块时，将错误信息存储在静态文件中。 版权所有（C）2004，JPO

公开(公告)号：GB2368314B

公开(公告)日：2005-03-16

申请号：GB0125657

申请日：2001-10-25

Applicant: INFINEON TECHNOLOGIES AG

Inventor： ADLER FRANK ,  ANGENENDT GUIDO

IPC: C23F1/02 ,  C23F1/08 ,  H01L21/00 ,  H01L21/311 ,  H01L21/3213

Abstract: A method is described for local etching of surfaces. The method includes the steps of providing a surface, providing an etchant, and providing a device for supplying and extracting the etchant. The device contains two cylindrical lines of different cross-sectional areas, of which the cylindrical line with the smaller cross-sectional area is guided inside the cylindrical line with the larger cross-sectional area. An etchant is fed through the inner line to the region of the semiconductor wafer that is to be etched, and the etchant that spreads out beyond the region of the surface that is to be etched is extracted through the outer line. The cross-sectional area of the outer line is less than or equal to the area of the region of the surface which is to be etched.

公开(公告)号：DE10137345B4

公开(公告)日：2004-07-08

申请号：DE10137345

申请日：2001-07-31

Applicant: INFINEON TECHNOLOGIES AG

Inventor： ADLER FRANK ,  BERGER HARTMUT

IPC: G11C29/56 ,  G11C29/00 ,  G01R31/3193

Abstract: A test circuit for testing an integrated circuit, includes a test signal input for receiving a test signal from the integrated circuit and a reference signal input for receiving a reference signal. A comparator is in communication with the test signal input and with the reference signal input. The comparator is configured to provide, at a comparator output, an error signal if a comparison between the reference signal and the test signal indicates an error. The error signal, if present, is stored in an error memory, in communication with the comparator output.

公开(公告)号：DE10134654A1

公开(公告)日：2003-02-13

申请号：DE10134654

申请日：2001-07-20

Applicant: INFINEON TECHNOLOGIES AG

Inventor： ADLER FRANK ,  VERSEN MARTIN

IPC: G01R27/28 ,  G01R31/00 ,  G01R31/14 ,  G06F19/00 ,  G11C29/00 ,  G11C29/56

Abstract: A computer system has at least one data defect memory, at least one address defect memory and also a test program. The computer system is connected to a memory module that has a memory space with defect-free and defective memory cells, a plurality of data lines, and a plurality of address lines. The addresses of the defective memory cells in the memory space and the data lines that are connected to the defective memory cells are determined from the information items of the address defect memory and also from the information items of the data defect memory.

公开(公告)号：DE10140757B4

公开(公告)日：2004-11-04

申请号：DE10140757

申请日：2001-08-20

Applicant: INFINEON TECHNOLOGIES AG

Inventor： ADLER FRANK ,  VERSEN MARTIN ,  MOSER MANFRED ,  HUBER THOMAS

IPC: G01R31/28 ,  G01R31/30 ,  G11C29/02 ,  G11C29/50 ,  G01R29/00

Abstract: Signal transit times on printed circuit boards which are equipped with all the passive components but without any active components can be determined using automatic standard test equipment composed of a standard test unit and a performance board with fittings attached thereto. In that first, using a standard routine of the test unit, a transit time is measured on the performance board from the CIF connector as far as the fitting, then a printed circuit board is plugged into the fitting location determined for it and then the sum transit time of the CIF connector is measured as far as the landing pad on the printed circuit board. By forming differences between the two measured values, the transit times on a printed circuit board can be measured with a high degree of precision with the automatic standard test equipment used in standard module testing technology.

公开(公告)号：DE10213881C1

公开(公告)日：2003-10-02

申请号：DE10213881

申请日：2002-03-27

Applicant: INFINEON TECHNOLOGIES AG

Inventor： ADLER FRANK ,  MOSER MANFRED

IPC: G11C5/04 ,  H01L23/31 ,  H01L23/36 ,  H01L25/065 ,  H01L21/98 ,  H01L21/60 ,  H01L21/58 ,  H05K3/32

Abstract: The memory module has an electronic circuit board (10) provided with a pair of semiconductor chips (20,25) stacked one on top of the other on one side of the circuit board, each chip having an integrated circuit (21,26) on its front side, the chips secured together on their rear sides, with bonding wires (28) between the integrated circuit of the upper chip and the circuit board. The underlying chip is fitted in a recess in the surface of the circuit board provided with bonding surface contacts (15) electrically coupled to the circuit board. An Independent claim for a manufacturing method for a memory module is also included.

公开(公告)号：DE10213879C1

公开(公告)日：2003-07-10

申请号：DE10213879

申请日：2002-03-27

Applicant: INFINEON TECHNOLOGIES AG

Inventor： ADLER FRANK ,  HANISCH CHRISTIAN ,  MOSER MANFRED

IPC: H01L21/60 ,  H01L23/13 ,  H01L23/538 ,  H05K1/18 ,  H01L21/58 ,  H05K3/32

Abstract: The electronic component has an electronic circuit board (10) and at least one semiconductor chip (20) provided with an integrated circuit (21), fitting into a recess (15) provided in the surface of the electronic circuit board. The width and length of the recess corresponds to the size of the base surface of the semiconductor chip, with side elements for gripping the inserted semiconductor chip in the correct position for mechanical and electrical connection with the electronic circuit board.

公开(公告)号：DE10213009A1

公开(公告)日：2003-10-09

申请号：DE10213009

申请日：2002-03-22

Applicant: INFINEON TECHNOLOGIES AG

Inventor： ADLER FRANK ,  THIELE FRANK ,  FOERSTE MARKUS

IPC: G06F12/16 ,  G01R31/26 ,  G11C29/56 ,  H01L21/66 ,  G11C29/00

Abstract: A method for electronically testing at least one memory module involves initially connecting the module to be tested to the computer system, electronically reading-in computer system configuration data, and then inputting a memory-module identifier for each memory module connected to the computer. An electronic comparison is made between the number of modules connected to the computer system and the number of memory module identifiers. Test information for the module being tested is then read in, followed by electronic testing of the module and the test results are automatically evaluated. If at least one module is faulty the erroneous data is electronically stored in at least one statistics data file. An Independent claim is given for a computer program product, as well as a computer program, for carrying out the electronic testing procedure.

公开(公告)号：DE10203570A1

公开(公告)日：2003-08-14

申请号：DE10203570

申请日：2002-01-30

Applicant: INFINEON TECHNOLOGIES AG

Inventor： ADLER FRANK ,  MOSER MANFRED ,  HUBER THOMAS

IPC: G11C29/02 ,  G11C29/00

Abstract: The method involves making read and write accesses to the semiconducting component by writing a first information item by driving a memory address so no address lines (L1-6) are electrically biased, writing a different second item, whereby a second address is selected so that only one address line is biased, reading the first memory address, which is driven so no address lines are biased, and checking which information item was read out.

公开(公告)号：DE10053198C2

公开(公告)日：2003-01-02

申请号：DE10053198

申请日：2000-10-26

Applicant: INFINEON TECHNOLOGIES AG

Inventor： ADLER FRANK ,  ANGENENDT GUIDO

IPC: C23F1/02 ,  C23F1/08 ,  H01L21/00 ,  H01L21/311 ,  H01L21/3213 ,  H01L21/306

Abstract: A method is described for local etching of surfaces. The method includes the steps of providing a surface, providing an etchant, and providing a device for supplying and extracting the etchant. The device contains two cylindrical lines of different cross-sectional areas, of which the cylindrical line with the smaller cross-sectional area is guided inside the cylindrical line with the larger cross-sectional area. An etchant is fed through the inner line to the region of the semiconductor wafer that is to be etched, and the etchant that spreads out beyond the region of the surface that is to be etched is extracted through the outer line. The cross-sectional area of the outer line is less than or equal to the area of the region of the surface which is to be etched.