2.
    发明专利
    未知

    公开(公告)号:DE102009044013A1

    公开(公告)日:2010-04-08

    申请号:DE102009044013

    申请日:2009-09-16

    Abstract: This disclosure relates to systems and methods for frequency to phase conversion using uniform sampling, where a uniform or constant clock period is used.

    4.
    发明专利
    未知

    公开(公告)号:DE102004009613B4

    公开(公告)日:2010-05-12

    申请号:DE102004009613

    申请日:2004-02-27

    Abstract: A circuit arrangement ( 10 ) for compensating for nonlinearities (NL 1 , NL 2 ) from analog/digital converters ( 15, 16 ) operating with different timing, having at least two analog/digital converters ( 15, 16 ) which are each clocked with different timing and which each have a predetermined nonlinear converter characteristic with integral nonlinearities (NL 1 , NL 2 ), and which accept an analog input signal (VIN) applied to an input ( 11 ) on the circuit arrangement and respectively convert it into a digital intermediate signal (Z 1 , Z 2 ); and having a multiplexer ( 22 ) which is arranged downstream of the analog/digital converters and which successively switches through the digital intermediate signals (Z 1 , Z 2 ) in order to produce a digital output signal (ZD) from the circuit arrangement ( 10 ); where at least one of the nonlinear converter characteristics of the various analog/digital converters ( 15, 16 ) is predetermined such that after the intermediate signals have been combined in the multiplexer ( 22 ) the integral nonlinearities (NL 1 , NL 2 ) in the various analog/digital converters ( 15, 16 ) essentially compensate for one another.

    6.
    发明专利
    未知

    公开(公告)号:DE102004009613A1

    公开(公告)日:2005-11-17

    申请号:DE102004009613

    申请日:2004-02-27

    Abstract: A circuit arrangement ( 10 ) for compensating for nonlinearities (NL 1 , NL 2 ) from analog/digital converters ( 15, 16 ) operating with different timing, having at least two analog/digital converters ( 15, 16 ) which are each clocked with different timing and which each have a predetermined nonlinear converter characteristic with integral nonlinearities (NL 1 , NL 2 ), and which accept an analog input signal (VIN) applied to an input ( 11 ) on the circuit arrangement and respectively convert it into a digital intermediate signal (Z 1 , Z 2 ); and having a multiplexer ( 22 ) which is arranged downstream of the analog/digital converters and which successively switches through the digital intermediate signals (Z 1 , Z 2 ) in order to produce a digital output signal (ZD) from the circuit arrangement ( 10 ); where at least one of the nonlinear converter characteristics of the various analog/digital converters ( 15, 16 ) is predetermined such that after the intermediate signals have been combined in the multiplexer ( 22 ) the integral nonlinearities (NL 1 , NL 2 ) in the various analog/digital converters ( 15, 16 ) essentially compensate for one another.

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