公开(公告)号：DE10353926A1

公开(公告)日：2005-06-02

申请号：DE10353926

申请日：2003-11-18

Applicant: INFINEON TECHNOLOGIES AG

Inventor： WAGNER MICHAEL ,  SELZ MANFRED

IPC: G06F17/50 ,  H01L21/768

Abstract: Wiring elements are placed in a row with their components in a layout and linked among each other to connection wires. The resulting layout provides the structure for a semiconductor component. The wiring elements each have inputs (a,b) and outputs (c) for the connection wires and a driver, on which driver intensity is adjusted.

公开(公告)号：DE59912177D1

公开(公告)日：2005-07-21

申请号：DE59912177

申请日：1999-08-05

Applicant: INFINEON TECHNOLOGIES AG

Inventor： SCHNEIDER HELMUT ,  WAGNER MICHAEL

IPC: G11C7/12 ,  H01L21/8242 ,  H01L27/108

Abstract: A combined precharging and homogenizing circuit for a semiconductor memory configuration made up of a memory cell array having a multiplicity of bit line pairs. The combined precharging and homogenizing circuit containing a first and a second field-effect precharging transistor and a homogenizing transistor connected in series between the two precharging transistors. Gates of the two precharging transistors and of the homogenizing transistor are connected together to form a common gate. Sources of the precharging transistors are connected together to form a common source. A drain of the first precharging transistor and a drain of the homogenizing transistor are connected together to form a common drain and the source of the homogenizing transistor and the drain of the second precharging transistor are connected together to form a common source/drain. In the combined precharging and homogenizing circuit, the invention provides that the common gate is angled and is configured rotated through about 45 DEG in relation to a longitudinal direction of the bit lines. In addition, the common drain and the common source/drain are drawn forward beyond the common gate defining protruding regions, and that bit line contacts are accommodated in the protruding regions.

公开(公告)号：DE10231647A1

公开(公告)日：2003-10-23

申请号：DE10231647

申请日：2002-07-12

Applicant: INFINEON TECHNOLOGIES AG

Inventor： WAGNER MICHAEL ,  MOSLER SEBASTIAN

IPC: H01L23/485 ,  H01L23/50

Abstract: The device has first and second contact surfaces arranged in adjacent first and second rows, whereby the first and second contact surfaces each have at least one edge. The first and second contact surfaces are arranged so that an edge of the first and an edge of the second are facing each other and are offset so that the first row of first contact surfaces and the second row of second contact surfaces are transversely meshed with each other. Independent claims are also included for the following: (1) an integrated circuit with an inventive arrangement; (2) a contact surface for an integrated circuit.

公开(公告)号：DE10209073A1

公开(公告)日：2003-09-18

申请号：DE10209073

申请日：2002-02-28

Applicant: INFINEON TECHNOLOGIES AG

Inventor： WAGNER MICHAEL ,  SELZ MANFRED

IPC: H01L23/528 ,  H01L27/118 ,  H01L23/522

Abstract: A semiconductor chip has standard cells which are disposed in a plurality of mutually adjacent rows, wiring channels are disposed between the rows and at at least one location along at least one wiring channel, the width of the wiring channel determined by a prescribed unambiguous and variable assignment specification. The width of the wiring channels can thus be varied in a flexible manner, so that a circuit can be fabricated in a space-saving manner.

公开(公告)号：DE10348167A1

公开(公告)日：2005-03-10

申请号：DE10348167

申请日：2003-10-16

Applicant: INFINEON TECHNOLOGIES AG

Inventor： WAGNER MICHAEL ,  SELZ MANFRED

IPC: H01L21/768 ,  H01L27/118

Abstract: Method for wiring circuit elements in an integrated circuit has the following steps: provision of a network list that describes an electrical connection line between the output of a circuit element and inputs from one or more further circuit elements in the integrated circuit; dimensioning of the circuit element and further circuit elements so that the output driver strength of the output of the circuit element for driving the entire load is matched to the inputs of a further circuit element. The cross section of the connection line is dimensioned based on the output driver strength. An independent claim is made for an integrated circuit, especially an integrated memory circuit, wherein wiring dimensions are matched to circuit loading.

公开(公告)号：DE102004024784A1

公开(公告)日：2004-12-16

申请号：DE102004024784

申请日：2004-05-17

Applicant: INFINEON TECHNOLOGIES AG

Inventor： WAGNER MICHAEL

IPC: G06F17/50 ,  H01L21/822 ,  H01L27/118

Abstract: Circuit elements and their constituents are sequentially placed in physical lay-out and structured in semiconductor component with lay-out. Each element has driver with adjusted driver strength and connecting members. Parasitic interference sensibility of circuit elements is evaluated and circuit elements with highest susceptibility to parasitic interference are placed with shortest possible connecting members.

公开(公告)号：DE102004023646A1

公开(公告)日：2005-11-17

申请号：DE102004023646

申请日：2004-04-30

Applicant: INFINEON TECHNOLOGIES AG

Inventor： SELZ MANFRED ,  WAGNER MICHAEL ,  KEINER KLAUS

IPC: H01L21/8242 ,  H01L23/528 ,  H01L27/02 ,  H01L27/10

Abstract: The arrangement has a standard cell (1) and an open space (21, 22) for the connection for a cross connection (31, 32, 33) between a current supply and arranged on the edge of the standard cell. A first open space (21) connects between a second current supply (12) and the edge of the standard cell. The first open space is arranged for cross connection between a first current supply and the edge of the standard cell and a second open space (22) for connection to second cross connection (32) between a second current supply course and the edge of the standard cell.

公开(公告)号：DE10159699A1

公开(公告)日：2003-06-26

申请号：DE10159699

申请日：2001-12-05

Applicant: INFINEON TECHNOLOGIES AG

Inventor： KEINER KLAUS ,  WAGNER MICHAEL

IPC: G06F17/50 ,  H01L27/118