公开(公告)号：DE10159633A1

公开(公告)日：2003-06-26

申请号：DE10159633

申请日：2001-12-05

Applicant: INFINEON TECHNOLOGIES AG

Inventor： HENFTLING RENATE ,  ECKER WOLFGANG ,  ZINN ANDREAS ,  BAUER MATTHIAS ,  ZAMBALDI MARTIN

IPC: G01R31/3183 ,  G06F17/50

Abstract: The method involves connecting the circuit-under-test (101) to a test bench element (102a-102n) via a test logic verification layer (105) and/or applying at least one test logic verification element (105a). A control data stream (111a-111n) is supplied from a test bench controller (103) to the corresponding elements. Test signals are used to verify the circuit-under-test. The circuit-under-test is simulated when the test logic is verified, whereby test signals are applied from the test bench element to the circuit-under-test. An Independent claim is also included for an apparatus for simulating a circuit-under-test.

公开(公告)号：DE10160633C1

公开(公告)日：2003-06-18

申请号：DE10160633

申请日：2001-12-11

Applicant: INFINEON TECHNOLOGIES AG

Inventor： HENFTLING RENATE ,  ECKER WOLFGANG ,  ZINN ANDREAS ,  BAUER MATTHIAS ,  ZAMBALDI MARTIN

IPC: G06F11/26

Abstract: The method involves connecting a circuit unit to be verified to a test bench element (102a-102c) for supplying interface data streams (115a,115b,115c). A command memory unit (107) controlled by a test bench controller provides the test bench elements with command data streams. The test bench elements of the circuit unit to be verified and the test bench controller are clocked using a clock signal (105) from a controllable clock generator (106). A simulation result is output from the test bench elements after simulating the circuit unit to be verified, and stored in a result memory unit (108). The simulation result is evaluated in a computer unit. The clock generator (106) is controlled to maintain and recover the clock signal (105). An Independent claim is also included for an apparatus for simulating a circuit unit to be verified.

公开(公告)号：DE10161031C1

公开(公告)日：2003-04-17

申请号：DE10161031

申请日：2001-12-12

Applicant: INFINEON TECHNOLOGIES AG

Inventor： HENFTLING RENATE ,  ECKER WOLFGANG ,  ZINN ANDREAS ,  BAUER MATTHIAS ,  ZAMBALDI MARTIN

IPC: G06F11/26 ,  G06F17/50

Abstract: The method has a circuit module (101) to be verified connected to at least one test bench element (102a,..102n) via an adapter (301,302), with a control data stream fed to the test bench element from a test bench controller (103), for providing a corresponding data stream between the test bench element and the adapter, providing a signal level adaption for providing an interface data stream between the adapter and the circuit module. An Independent claim for a device for simulating and/or testing a circuit module is also included.

公开(公告)号：DE10161578C2

公开(公告)日：2003-05-08

申请号：DE10161578

申请日：2001-12-14

Applicant: INFINEON TECHNOLOGIES AG

Inventor： HENFTLING RENATE ,  ECKER WOLFGANG ,  ZINN ANDREAS ,  BAUER MATTHIAS ,  ZAMBALDI MARTIN

IPC: G06F11/26

公开(公告)号：DE10127170A1

公开(公告)日：2002-12-19

申请号：DE10127170

申请日：2001-06-05

Applicant: INFINEON TECHNOLOGIES AG

Inventor： HENFTLING RENATE ,  ECKER WOLFGANG ,  ZINN ANDREAS ,  BAUER MATTHIAS ,  ZAMBALDI MARTIN

IPC: G06F11/36

Abstract: The method involves associating different first fault location devices (5-7) with individual simulation models (2-4) describing a system to locate faults by accessing the relevant models, automatically detecting a user input with a second fault location device (11) superior to the first devices and automatically controlling the first devices from the second device depending on the user input to find a system fault by accessing the relevant model. AN Independent claim is also included for the following: a fault location method arrangement.

公开(公告)号：DE10122252B4

公开(公告)日：2006-05-04

申请号：DE10122252

申请日：2001-05-08

Applicant: INFINEON TECHNOLOGIES AG

Inventor： HENFTLING RENATE ,  ECKER WOLFGANG ,  ZINN ANDREAS ,  BAUER MATTHIAS ,  PILSL MICHAEL ,  ZAMBALDI MARTIN

IPC: G06F17/50 ,  G01R31/3183

公开(公告)号：DE10158807C1

公开(公告)日：2003-06-26

申请号：DE10158807

申请日：2001-11-30

Applicant: INFINEON TECHNOLOGIES AG

Inventor： HENFTLING RENATE ,  ZINN ANDREAS ,  ECKER WOLFGANG ,  BAUER MATTHIAS ,  ZAMBALDI MARTIN

IPC: G06F11/26 ,  G06F17/50

Abstract: The simulation testing method uses at least one configuration stage for configuration of each data stream transferred between at least one test bench element (102a-102n) and a tested circuit module (101), at least one control data stream supplied to the test bench element from a test bench controller (103), for execution of corresponding operations and supply of at least one test bench element configuration data stream to the configuration stage. An Independent claim for a device for configuration of data streams transferred between test bench elements and a tested circuit module is also included.

公开(公告)号：DE10161578A1

公开(公告)日：2002-12-12

申请号：DE10161578

申请日：2001-12-14

Applicant: INFINEON TECHNOLOGIES AG

Inventor： HENFTLING RENATE ,  ECKER WOLFGANG ,  ZINN ANDREAS ,  BAUER MATTHIAS ,  ZAMBALDI MARTIN

IPC: G06F11/26 ,  G06F11/22

Abstract: The method involves connecting the circuit unit (101) to at least one test bench element shell (201) to pass/switch interface data streams from the circuit unit, connecting the shell to test bench elements (102a...) to pass data streams from these elements to the circuit unit, controling the shell using a control data stream from a test bench controler and evaluating the interface data stream through the shell to check circuit unit functionality. AN Independent claim is also included for the following: a shell arrangement for simulating and testing a circuit unit to be verified.

公开(公告)号：DE10125364A1

公开(公告)日：2002-12-05

申请号：DE10125364

申请日：2001-05-23

Applicant: INFINEON TECHNOLOGIES AG

Inventor： HENFTLING RENATE ,  ECKER WOLFGANG ,  ZINN ANDREAS ,  BAUER MATTHIAS ,  PILSL MICHAEL ,  ZAMBALDI MARTIN

IPC: G01R31/3181 ,  G01R31/3183 ,  G06F17/50 ,  G06F11/263

Abstract: Method for simulation of a circuit unit (101) that is to be verified using a test arrangement, using a signal simulation flow of pre-defined test patterns, with the following steps: (a) leading off of at least one test cycle to a test arrangement that includes a circuit unit to be tested (b) determination of an active signal flank of the test cycle (c) receipt of a test pattern from the test arrangement (d) adjustment of signal delay times (e) generation of a simulation signal flow (f) supply of the signal flow to the unit being tested.

公开(公告)号：DE10122252A1

公开(公告)日：2002-11-21

申请号：DE10122252

申请日：2001-05-08

Applicant: INFINEON TECHNOLOGIES AG

Inventor： HENFTLING RENATE ,  ECKER WOLFGANG ,  ZINN ANDREAS ,  BAUER MATTHIAS ,  PILSL MICHAEL ,  ZAMBALDI MARTIN

IPC: G01R31/3183 ,  G06F17/50

Abstract: Method for simulating a circuit unit (101) so that it can be verified using a test arrangement with which interface data streams (P0(0)-P0(7), P1(0)-P1(7)) are delayed. Method has the following steps: connection of the circuit unit under test to a time delay shell (301, 302) through which the data streams are passed, supply of a control data stream (111a-111n) from the test bench controller (103) and delay of the interface data streams and the test data stream (112, 113) through the delay shell according to an adjustable test input. The invention also relates to a corresponding time delay shell for implementation of the inventive method.