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    TEST ENVIRONMENT FOR TESTING ELECTRONIC SYSTEMS AND METHOD FOR TESTING SYSTEMS BY MEANS OF A TEST ENVIRONMENT
    1.
    发明申请
    TEST ENVIRONMENT FOR TESTING ELECTRONIC SYSTEMS AND METHOD FOR TESTING SYSTEMS BY MEANS OF A TEST ENVIRONMENT 审中-公开
    测试环境用于分析测试系统，电子系统和方法通过测试环境

    公开(公告)号：WO0137089A2

    公开(公告)日：2001-05-25

    申请号：PCT/DE0004050

    申请日：2000-11-17

    Applicant: INFINEON TECHNOLOGIES AG ,  BAUER MATTHIAS ,  HENFTLING RENATE ,  ECKER WOLFGANG

    Inventor： BAUER MATTHIAS ,  HENFTLING RENATE ,  ECKER WOLFGANG

    IPC: G06F17/50 ,  G06F11/00

    CPC classification number: G06F17/5022

    Abstract: The invention relates to a test environment that is divided up into sections that are different from one another. At least a part of the environment maintains the communication with a main controller and at least one further part generates the commands for the electronic system to be tested. The part that maintains the communication to the main controller consists of at least partially programmable components and the part that generates the stimuli is designed such that the generation of the stimuli is carried out on at least one hardware accelerator and/or at least one cycle-based simulator.

    Abstract translation: 本发明涉及一种用于电子系统的研究，其中所述的测试环境是这样的，它产生测试向量的测试环境。 根据本发明的测试环境被分成相互不同的部分，至少一部分保持与主控制器，其中，至少一个另外的部分生成用于测试的电子系统的命令的通信，其特征在于，与主控制器保持通信的部分 至少部分地由可编程组件，并且其中所述至少一个硬件加速器的刺激的一部分，和/或至少一种基于周期的模拟器进行。

    VERFAHREN ZUM PROGRAMMIEREN EINER RESISTIVEN SPEICHERZELLE UND RESISTIVE SPEICHERVORRICHTUNG
    4.
    发明专利
    VERFAHREN ZUM PROGRAMMIEREN EINER RESISTIVEN SPEICHERZELLE UND RESISTIVE SPEICHERVORRICHTUNG 未知

    公开(公告)号：DE102017116737A1

    公开(公告)日：2019-01-31

    申请号：DE102017116737

    申请日：2017-07-25

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： STRENZ ROBERT ,  ALLINGER ROBERT ,  BAUER MATTHIAS ,  BUKETHAL CHRISTOPH ,  HOFMANN KARL ,  PISSORS VOLKER

    IPC: G11C13/00

    Abstract: Es wird ein Verfahren zum Programmieren einer resistiven Speicherzelle bereitgestellt. Die Speicherzelle kann wenigstens einen ersten und einen zweiten Zustand aufweisen, wobei der erste und der zweite Zustand komplementäre Zustände sein können. Beim Verfahren kann als ein Analogwert oder ein Wert aus mehreren Digitalwerten wenigstens ein physikalischer Parameterwert der resistiven Speicherzelle im ersten Zustand bestimmt werden, auf der Grundlage des bestimmten wenigstens einen physikalischen Parameterwerts der resistiven Speicherzelle im ersten Zustand eine Programmierenergie bestimmt werden, die zum Programmieren der resistiven Speicherzelle aus dem ersten Zustand in den zweiten Zustand bereitzustellen ist, und ein Programmierpuls angewendet werden, wodurch die bestimmte Programmierenergie zugeführt wird, wodurch die resistive Speicherzelle in den zweiten Zustand programmiert wird.

    6.
    发明专利
    未知

    公开(公告)号：DE10127170A1

    公开(公告)日：2002-12-19

    申请号：DE10127170

    申请日：2001-06-05

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： HENFTLING RENATE ,  ECKER WOLFGANG ,  ZINN ANDREAS ,  BAUER MATTHIAS ,  ZAMBALDI MARTIN

    IPC: G06F11/36

    Abstract: The method involves associating different first fault location devices (5-7) with individual simulation models (2-4) describing a system to locate faults by accessing the relevant models, automatically detecting a user input with a second fault location device (11) superior to the first devices and automatically controlling the first devices from the second device depending on the user input to find a system fault by accessing the relevant model. AN Independent claim is also included for the following: a fault location method arrangement.

    A method for simulation of circuit units, such as microprocessors and graphics cards, being verified, involves using test benches/models or circuit simulation models
    7.
    发明专利
    A method for simulation of circuit units, such as microprocessors and graphics cards, being verified, involves using test benches/models or circuit simulation models 未知

    公开(公告)号：DE10124175A1

    公开(公告)日：2002-11-28

    申请号：DE10124175

    申请日：2001-05-17

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： HENFTLING RENATE ,  ECKER WOLFGANG ,  ZINN ANDREAS ,  BAUER MATTHIAS

    IPC: G06F17/50

    Abstract: A method for simulating a circuit unit (101) by an arrangement with self-registering test bench elements (102a..102n) connecting the circuit unit to the simulation arrangement. Method involves connecting the circuit unit being verified via at least one self-registering test bench element, and supplying a control data flow (111) from the test bench controller (103) to the circuit unit being verified, via a test bench element, and then delivering a test bench element data flow from the test bench element to an associated self-registering element (105,106) of the simulation arrangement and then supplying a self-registering data flow to the test bench controller (103) of the simulation arrangement, and driving the test bench element by the test-bench controller (103) with the control data flow (111). An Independent claim is given for a device for self-registering of test bench elements.

    8.
    发明专利
    未知

    公开(公告)号：DE10065508A1

    公开(公告)日：2002-07-18

    申请号：DE10065508

    申请日：2000-12-28

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： HENFTLING RENATE ,  ECKER WOLFGANG ,  ZINN ANDREAS ,  BAUER MATTHIAS

    IPC: G01R31/319 ,  G06F17/50 ,  G06F11/263 ,  G11C29/00

    Abstract: The invention relates to a method for testing electronic systems, according to which a test environment (1) is configured in such a way that it generates stimuli, which trigger a reaction in the system (3) to be tested. The test environment (1) has a plurality of test bench elements (11, 12, 13), which emit stimuli via a respective line (9), or receive reaction signals of the system (3). The test bench elements (11, 12, 13) have a respective memory (17) for saving test commands and a generator (19) for generating the stimuli or for evaluating the reaction signal, said generator (19) executing the test commands.

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