公开(公告)号：DE102005038736A1

公开(公告)日：2007-03-01

申请号：DE102005038736

申请日：2005-08-16

Applicant: INFINEON TECHNOLOGIES AG

Inventor： HINZ TORSTEN ,  JAKOBS ANDREAS ,  ZARYOUH BENAISSA

IPC: H03K5/13

Abstract: Each delay line (2,3) has cascaded delay components (4) that form a U-shaped signal path. A phase comparator (PD) receives an input clock pulse (CLKIN) and a signal from one of the delay lines. The phase comparator provides an output to the control inputs (DLCTR) of the delay components while the input clock pulse is also received by the delay line (2) such that a feedback loop is formed. An input signal (SIGIN) is input, not to the delay line whose signal output (OUT1,OUT2) is connected to the phase comparator, to produce an output signal (SIGOUT).

公开(公告)号：DE102005008151A1

公开(公告)日：2006-08-24

申请号：DE102005008151

申请日：2005-02-23

Applicant: INFINEON TECHNOLOGIES AG

Inventor： JAKOBS ANDREAS ,  HINZ TORSTEN ,  ZARYOUH BENAISSA

IPC: H03L7/081

Abstract: Controllable delay elements (6) in series form delay chain (2) and phase detector (3) generates control signal, dependent on periodic input signal, and periodic signal delayed by delay chain.Circuit contains selection unit (7), coupled to each delay element to apply output signal of element to output of DLL circuit. Compensation circuit (9-11) modifies selection signal (AS) so that additional delay between periodic input and output signal of DLL circuit is compensated.

公开(公告)号：DE102005008151B4

公开(公告)日：2008-02-28

申请号：DE102005008151

申请日：2005-02-23

Applicant: INFINEON TECHNOLOGIES AG

Inventor： JAKOBS ANDREAS ,  HINZ TORSTEN ,  ZARYOUH BENAISSA

IPC: H03L7/081

Abstract: Controllable delay elements (6) in series form delay chain (2) and phase detector (3) generates control signal, dependent on periodic input signal, and periodic signal delayed by delay chain.Circuit contains selection unit (7), coupled to each delay element to apply output signal of element to output of DLL circuit. Compensation circuit (9-11) modifies selection signal (AS) so that additional delay between periodic input and output signal of DLL circuit is compensated.