公开(公告)号：WO2004066167B1

公开(公告)日：2005-03-10

申请号：PCT/EP2004000582

申请日：2004-01-23

Applicant: INFINEON TECHNOLOGIES AG ,  MIELENZ CARSTEN ,  ZETTLER THOMAS

Inventor： MIELENZ CARSTEN ,  ZETTLER THOMAS

IPC: G06F17/50

CPC classification number: G06F17/5009 ,  G06F2217/14 ,  G06F2217/78 ,  G06F2217/86

Abstract: The invention relates to a method for supplying and optimizing a virtual prototype, especially an integrated circuit or a system, said integrated circuit or system and/or an application software that is provided therefor being divided into a plurality of transactions, each of which characterizes a part of the integrated circuit or system associated therewith or a software element. According to the inventive method, one weighting element representing the power consumption of the corresponding part or software element is assigned to a transaction, and the performance is calculated.

Abstract translation: 本发明涉及一种方法，用于为集成电路或系统，其中所述集成电路或系统和/或专用的应用软件被划分成多个交易，并且交易的每个部署和优化虚拟原型，特别是 一个她的集成电路或系统或特征的软件元件，其特征在于它是在一个配重元件被分配每一种情况下，这是各个部分的或软件项的功率消耗，并且所执行的功率计算交易的zugeordnenten一部分。

公开(公告)号：WO2004066167A3

公开(公告)日：2005-01-06

申请号：PCT/EP2004000582

申请日：2004-01-23

Applicant: INFINEON TECHNOLOGIES AG ,  MIELENZ CARSTEN ,  ZETTLER THOMAS

Inventor： MIELENZ CARSTEN ,  ZETTLER THOMAS

IPC: G06F17/50

CPC classification number: G06F17/5009 ,  G06F2217/14 ,  G06F2217/78 ,  G06F2217/86

Abstract: The invention relates to a method for supplying and optimizing a virtual prototype, especially an integrated circuit or a system, said integrated circuit or system and/or an application software that is provided therefor being divided into a plurality of transactions, each of which characterizes a part of the integrated circuit or system associated therewith or a software element. According to the inventive method, one weighting element representing the power consumption of the corresponding part or software element is assigned to a transaction, and the performance is calculated.

Abstract translation: 本发明涉及一种用于提供和优化虚拟原型的方法，特别是用于集成电路或系统，其中集成电路或系统和/或专用应用软件被分成多个交易和交易 表征与其关联的集成电路或系统的一部分或其中权重元素被分配给交易的软件元件，其表示相应部分或软件元件的功耗，并且执行功率计算。

公开(公告)号：WO2004064477A3

公开(公告)日：2004-12-29

申请号：PCT/DE2004000057

申请日：2004-01-16

Applicant: INFINEON TECHNOLOGIES AG ,  ENDRES HEINZ ,  ZETTLER THOMAS

Inventor： ENDRES HEINZ ,  ZETTLER THOMAS

IPC: G06F1/10 ,  G06F17/50

CPC classification number: G06F17/5045 ,  G06F1/10

Abstract: Disclosed is a method for creating a timing hierarchy in an integrated semiconductor circuit comprising a sequential circuit that is provided with at least two synchronous switching elements with respective timing circuits. The inventive method comprises the following steps: synchronous switching elements having uncritical switching prerequisites regarding a signal arrival time relative to a clock pulse arrival time are determined; the clock pulse arrival time is delayed with the aid of at least one delaying element located in the timing circuit of at least one synchronous switching element having uncritical switching prerequisites so as to minimize the number of synchronous switching elements that simultaneously change the switching mode.

Abstract translation: 一种用于创建具有含具有切换机构具有以下步骤各自的时钟线的至少两个同步的开关元件中的半导体集成电路的时钟树结构的方法。 有相对于​​非关键Umschaltvoraussetzungen信号到达时间相对于到来的时钟时间来确定同步的开关元件。 该时钟信号的到达时间将与至少一个延迟元件的在时钟线中最小化的同时改变所述同步开关元件的开关状态的数量的意义上，借助于至少一个同步开关元件的与非关键Umschaltvoraussetzungen移动。

公开(公告)号：DE50303142D1

公开(公告)日：2006-06-01

申请号：DE50303142

申请日：2003-12-13

Applicant: INFINEON TECHNOLOGIES AG

Inventor： ZETTLER THOMAS

IPC: G01R31/3185 ,  G01R31/28 ,  G01R31/316 ,  H01L23/544

Abstract: An integrated circuit and an associated packaged integrated circuit are provided which improve testability and reduce the test costs. The integrated circuit contains an integrated functional circuit to be tested, a test interface that connects the functional circuit to a test apparatus which performs a function test on the functional circuit to ascertain a test result, and an integrated self-marking apparatus that produces a marking on the basis of the test result. The marking can be magnetic or optical or electrical, volatile or nonvolatile, and thermally or electrically activated. The test apparatus includes an external test unit or an integrated self-test unit. Nonvolatile memory elements store the test results in a buffer.

公开(公告)号：DE10302795B4

公开(公告)日：2006-03-09

申请号：DE10302795

申请日：2003-01-24

Applicant: INFINEON TECHNOLOGIES AG

Inventor： ZETTLER THOMAS ,  MIELENZ CARSTEN

IPC: G06F17/50

公开(公告)号：DE10301696A1

公开(公告)日：2004-08-05

申请号：DE10301696

申请日：2003-01-17

Applicant: INFINEON TECHNOLOGIES AG

Inventor： ZETTLER THOMAS ,  ENDRES HEIN

IPC: G06F1/10 ,  G06F17/50

公开(公告)号：DE10258511A1

公开(公告)日：2004-07-08

申请号：DE10258511

申请日：2002-12-14

Applicant: INFINEON TECHNOLOGIES AG

Inventor： ZETTLER THOMAS

IPC: G01R31/28 ,  G01R31/3185 ,  H01L23/544 ,  H01L21/66

Abstract: An integrated circuit and an associated packaged integrated circuit are provided which improve testability and reduce the test costs. The integrated circuit contains an integrated functional circuit to be tested, a test interface that connects the functional circuit to a test apparatus which performs a function test on the functional circuit to ascertain a test result, and an integrated self-marking apparatus that produces a marking on the basis of the test result. The marking can be magnetic or optical or electrical, volatile or nonvolatile, and thermally or electrically activated. The test apparatus includes an external test unit or an integrated self-test unit. Nonvolatile memory elements store the test results in a buffer.

公开(公告)号：AT239302T

公开(公告)日：2003-05-15

申请号：AT97914128

申请日：1997-02-06

Applicant: INFINEON TECHNOLOGIES AG

Inventor： ZETTLER THOMAS ,  WINNERL JOSEF ,  GEORGAKOS GEORG ,  POCKRANDT WOLFGANG

IPC: H01L21/82 ,  B29C65/02 ,  B29L31/26 ,  H01L23/525 ,  H01L23/535 ,  H01L27/02

Abstract: The invention relates to a separable connecting bridge (fuse) with an electrically conductive, longitudinally continuous conductive track (1) of a given width transversely to its length of a second type of conductivity opposite to the first, said track being formed in a substrate (2, 2a) of a first type of conductivity, where the semiconductor material of the first type of conductivity has a concentration in relation to the material of the conductive track such that, at a predetermined activation temperature which is higher than the operating temperature of the connecting bridge (12, 13), an interruption takes place over the entire width (m) of the conductive track (1) through the diffusion of the semiconductor material of the first type of conductivity and/or the material of the conductive track (1) of the second type of conductivity. 00000

公开(公告)号：ES2157666T3

公开(公告)日：2001-08-16

申请号：ES98936116

申请日：1998-06-08

Applicant: INFINEON TECHNOLOGIES AG

Inventor： ZETTLER THOMAS

IPC: G11C16/06 ,  G11C15/00 ,  G11C16/10

Abstract: A drive circuit for a non-volatile semiconductor storage configuration. The drive circuit having a level converter circuit which applies an output value and a complementary output value complementary to the output value to a bit line and/or a word line of the semiconductor storage configuration. The drive circuit also has a latch circuit that temporarily stores the data to be stored in the semiconductor storage configuration, and lies between an input circuit and the level converter circuit.

公开(公告)号：DE59800964D1

公开(公告)日：2001-08-09

申请号：DE59800964

申请日：1998-01-30

Applicant: INFINEON TECHNOLOGIES AG

Inventor： ZETTLER THOMAS

IPC: G11C29/04 ,  G06F11/20 ,  G06F12/16 ,  G11C16/08 ,  G11C29/00

Abstract: The invention relates to a memory characterized in that it comprises at least one memory cell array containing memory cells, a redundancy circuit containing at least one redundancy memory cell, and a redundancy-selecting line selector circuit having at least one allocation memory in which allocation information can be stored, whereby on the basis of said allocation information at least one redundancy memory cell can be assigned to at least one memory cell. In addition, the allocation memory has an allocation memory cell with an intermediate memory for storing the allocation information. Depending on the programming method used, known memories require relatively long programming periods for assigning redundancy memory cells to memory cells. In the case of the memories provided for by the invention, the allocation information can be transferred from the intermediate memory to the allocation memory cell, thus making it possible for redundancy memory cells to be assigned to defective memory cells rapidly and in an energy-efficient manner.