1.
    发明专利
    未知

    公开(公告)号:AT356436T

    公开(公告)日:2007-03-15

    申请号:AT98115621

    申请日:1998-08-19

    Abstract: Single-layer-in-semiconductor-substrate type semiconductor chip has circuits (T1,T2) arranged in at least one group with signal conductors (Vss,Vdd,SL1,SL2) extending in at least one wiring place (3) above the circuits (T1,T2). The supply- and signal-conductors (Vss,Vdd,SL1,SL2) in at least one wiring plane (3) over at least one circuit group have the greatest possible width, so that the spacing between each two conductors at the most is approx. twice the minimum possible spacing realisable by available technology, or more specifically approx. the minimum realisable spacing, using available technology.

    PROCEDIMIENTO Y DISPOSICION PARA EL FUNCIONAMIENTO DE UN CONTADOR DE ETAPAS MULTIPLES EN UN SENTIDO DE RECUENTO.

    公开(公告)号:ES2222941T3

    公开(公告)日:2005-02-16

    申请号:ES00993194

    申请日:2000-11-27

    Abstract: Procedimiento para el funcionamiento de un contador (11) de etapas múltiples en un solo sentido de recuento, siendo modificado el valor de recuento de un contador auxiliar (1) de una etapa, variable solamente en un sentido de recuento, en estados predeterminados del valor objetivo del contador (11) de varias etapas y siendo registrados los estados del valor de recuento del contador (11) de etapas múltiples y del contador (1) de una etapa, caracterizado por - la combinación del estado del valor de recuento del contador auxiliar (1) con datos adicionales para formar primeros datos de autenticidad, - la transmisión de los primeros datos de autenticidad junto con el valor de recuento del contador (11) de etapas múltiples hacia un dispositivo de verificación (4), - la recuperación del valor de recuento del contador auxiliar (1) en el dispositivo de verificación (4), - la generación de segundos datos de autenticidad a través de la combinación del valor de recuento recuperado del contador auxiliar (1) con los datos adicionales y - la comparación de los primeros datos de autenticidad con los segundos datos de autenticidad.

    3.
    发明专利
    未知

    公开(公告)号:DE50006767D1

    公开(公告)日:2004-07-15

    申请号:DE50006767

    申请日:2000-11-27

    Abstract: A method for operating a multistage counter in only one counting direction is described. The counting value of a single-stage auxiliary counter that can be changed in only one counting direction is changed in predetermined counting values of the multistage counter. The respective counting value states of the multistage counter and of the single-stage auxiliary counter are registered. First authenticity data is generated by logically linking the counting value of the auxiliary counter to supplementary data.

    4.
    发明专利
    未知

    公开(公告)号:AT249119T

    公开(公告)日:2003-09-15

    申请号:AT99947298

    申请日:1999-09-09

    Abstract: A method for authenticating at least one subscriber during a data interchange between at least two subscribers is described. In the method, a first subscriber transmits a first data item (a challenge signal) to a second subscriber, the second subscriber processes the first data item using an algorithm to give a second data item and transmits it to the first subscriber, which checks it for its correctness. At the same time as the first data item is being processed using the algorithm, at least one other processing operation on the first data item is carried out.

    5.
    发明专利
    未知

    公开(公告)号:BR0108090A

    公开(公告)日:2002-10-29

    申请号:BR0108090

    申请日:2001-01-26

    Abstract: The invention relates to a method and device for mutual authentication of two data processing units. The mutual authentication of two data processing units is normally carried out in two separate successive authentications. A challenge-response method is normally used. A first challenge is transmitted from a first data processing unit (1) to a second data processing unit (2) which sends back a first response. According to the invention, a second response is generated by the first data processing unit (1) and transmitted to the second data processing unit (2).

    6.
    发明专利
    未知

    公开(公告)号:DE59914864D1

    公开(公告)日:2008-10-16

    申请号:DE59914864

    申请日:1999-09-14

    Abstract: A circuit configuration includes at least one nonvolatile, electrically erasable and writable memory area. Each memory area is assigned a nonvolatile, electrically writable and erasable flag memory, which is connected through an address line, a programming line and an authentication line to the assigned memory area, a programming voltage source and a data verification circuit. In the event of an alteration in the content of a memory area, the state of the associated flag memory is changed and, after verification of the programmed memory area content, the flag memory is returned to its basic state.

    8.
    发明专利
    未知

    公开(公告)号:ES2214875T3

    公开(公告)日:2004-09-16

    申请号:ES99936340

    申请日:1999-05-28

    Abstract: A method of operating a multistage counter in only one counting direction includes the step of changing a counter reading of a single-stage auxiliary counter at given counter readings of the multistage counter. The single-stage auxiliary counter and the multistage counter can only be changed in one counting direction. Respective counter readings of the multistage counter and of the single-stage auxiliary counter are registered. Values of the respective counter readings of the single-stage auxiliary counter and of the multistage counter are compared with one another, and an indicator signal is generated based on a comparison result determined in the comparing step.

    10.
    发明专利
    未知

    公开(公告)号:ES2207285T3

    公开(公告)日:2004-05-16

    申请号:ES99947298

    申请日:1999-09-09

    Abstract: A method for authenticating at least one subscriber during a data interchange between at least two subscribers is described. In the method, a first subscriber transmits a first data item (a challenge signal) to a second subscriber, the second subscriber processes the first data item using an algorithm to give a second data item and transmits it to the first subscriber, which checks it for its correctness. At the same time as the first data item is being processed using the algorithm, at least one other processing operation on the first data item is carried out.

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