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    1.
    发明专利
    未知

    公开(公告)号：DE10310081A1

    公开(公告)日：2003-09-25

    申请号：DE10310081

    申请日：2003-03-07

    Applicant: INFINEON TECHNOLOGIES AG ,  IBM

    Inventor： FIFIELD JOHN A ,  HOKENMAIER WOLFGANG

    IPC: H03K19/00 ,  H03K19/003

    Abstract: A multiple finger off chip driver (OCD) has a single level translator for each of a plurality of PFET fingers and NFET fingers which allow the impedance of the OCD to be varied to match the impedance of a driven load. A plurality of PFET and NFET finger selection devices are used to select various combinations of output FETS and ballast resistor finger combinations to drive an output signal at a desired impedance level. The ballast resistors are scaled in ohmic value to the size of the output finger it is connected to. In this configuration, a constant ratio of FET impedance to ballast resistance is maintained in each drive stage (finger). By selecting various combinations of fingers various driver impedances can be selected.

    2.
    发明专利
    未知

    公开(公告)号：DE60027065D1

    公开(公告)日：2006-05-18

    申请号：DE60027065

    申请日：2000-01-21

    Applicant: IBM ,  INFINEON TECHNOLOGIES AG

    Inventor： CHU ALBERT M ,  FIFIELD JOHN A ,  ROTELLA JASON E ,  DORTU JEAN-MARC

    IPC: H03K5/15 ,  H03L7/081 ,  G11C7/22 ,  H03L7/095

    Abstract: A circuit and method are provided wherein a receiver receives an input train of pulses. The circuit includes a delay-locked-loop coupled to an output of the receiver. The delay-locked-loop includes a pulse generator responsive to received input train of pulses produced at the output of the receiver for producing first pulses in response to the leading edges of the received input train of pulses and second pulses in response to the trailing edges of received input train of pulses. The leading edge of the first pulse has the same edge type as the leading edge of the second pulse (i.e., the leading edge of the first pulse and the leading edge of the second pulse are either both rising edge types or both falling edges types). The first pulses and the second pulses are combined into a composite input signal comprising the first and second pulses with the leading edge of the first pulse maintaining the same edge type. The delay-locked-loop also includes a variable delay line fed by the composite input signal for producing a composite output train of pulses comprising both the first train of pulses and the second train of pulses after a selected time delay provided by the delay line. The delay-locked-loop is responsive to one of the first train of pulses and the second train of pulses in the composite output train of pulses for selecting the time delay of the variable delay line so as to produce the composite output train of pulses with a predetermined phase relationship to the input train of pulses.

    3.
    发明专利
    未知

    公开(公告)号：DE60027065T2

    公开(公告)日：2006-10-05

    申请号：DE60027065

    申请日：2000-01-21

    Applicant: IBM ,  INFINEON TECHNOLOGIES AG

    Inventor： CHU ALBERT M ,  FIFIELD JOHN A ,  ROTELLA JASON E ,  DORTU JEAN-MARC

    IPC: H03K5/15 ,  H03L7/081 ,  G11C7/22 ,  H03L7/095

    Abstract: A circuit and method are provided wherein a receiver receives an input train of pulses. The circuit includes a delay-locked-loop coupled to an output of the receiver. The delay-locked-loop includes a pulse generator responsive to received input train of pulses produced at the output of the receiver for producing first pulses in response to the leading edges of the received input train of pulses and second pulses in response to the trailing edges of received input train of pulses. The leading edge of the first pulse has the same edge type as the leading edge of the second pulse (i.e., the leading edge of the first pulse and the leading edge of the second pulse are either both rising edge types or both falling edges types). The first pulses and the second pulses are combined into a composite input signal comprising the first and second pulses with the leading edge of the first pulse maintaining the same edge type. The delay-locked-loop also includes a variable delay line fed by the composite input signal for producing a composite output train of pulses comprising both the first train of pulses and the second train of pulses after a selected time delay provided by the delay line. The delay-locked-loop is responsive to one of the first train of pulses and the second train of pulses in the composite output train of pulses for selecting the time delay of the variable delay line so as to produce the composite output train of pulses with a predetermined phase relationship to the input train of pulses.

    GAIN MEMORY CELL CIRCUIT
    6.
    发明专利
    GAIN MEMORY CELL CIRCUIT 失效

    公开(公告)号：JPH10241358A

    公开(公告)日：1998-09-11

    申请号：JP2699798

    申请日：1998-02-09

    Applicant: IBM

    Inventor： HOUGHTON RUSSELL J ,  BERTIN CLAUDE L ,  FIFIELD JOHN A ,  MILLER CHRISTOPHER P ,  TONTI WILLIAM R

    IPC: G11C11/402 ,  G11C11/403 ,  G11C11/405

    Abstract: PROBLEM TO BE SOLVED: To prevent read-out disturbance from an unselected cell by reading out a written word value stored on a storage node by means of a read transistor via a diode between bit lines. SOLUTION: When a write transistor Tw0 in a gain cell 20 is operated by a write-in word line WLW0, a value of a write-in bit line BLW0 is stored on the storage node SN0. When a read-out word line WLR0 is enabled to work, the read transistor Tr0 to be connected with the storage node SN0 in this case is connected via the diode D0 to a read-out bit line BLR0, so as to read out the stored value. The diode D0 is capable of preventing conductivity in the reverse direction of the read transistor Tr0, thus preventing disturbance from another cell, and also decreasing capacitance of the bit line. The same is the case with the other memory cells.

    ELECTRONICALLY PROGRAMMABLE ANTIFUSE AND CIRCUITS MADE THEREWITH
    7.
    发明申请
    ELECTRONICALLY PROGRAMMABLE ANTIFUSE AND CIRCUITS MADE THEREWITH 审中-公开
    电子可编程抗体和电路

    公开(公告)号：WO2005038869A3

    公开(公告)日：2006-02-09

    申请号：PCT/US2004032581

    申请日：2004-10-04

    Applicant: IBM ,  ABADEER WAGDI W ,  FIFIELD JOHN A ,  TONTI WILLIAM R

    Inventor： ABADEER WAGDI W ,  FIFIELD JOHN A ,  TONTI WILLIAM R

    IPC: H01L23/525 ,  H01L27/12 ,  H01L21/82 ,  H01L29/00

    CPC classification number: H01L23/5252 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

    Abstract: An antifuse device (120) that includes a bias element (124) and an programmable antifuse element (128) arranged in series with one another so as to form a voltage divider having an output node (F) located between the bias and antifuse elements. When the antifuse device is in its unprogrammed state, each of the bias element and antifuse element is non-conductive. When the antifuse device is in its programmed state, the bias element remains non-conductive, but the antifuse element is conductive. The difference in the resistance of the antifuse element between its unprogrammed state and programmed state causes the difference in voltages seen at the output node to be on the order of hundreds of mili-volts when a voltage of 1 V is applied across the antifuse device. This voltage difference is so high that it can be readily sensed using a simple sensing circuit.

    Abstract translation: 一种反熔丝装置（120），其包括彼此串联布置的偏置元件（124）和可编程反熔丝元件（128），以形成具有位于偏置和反熔丝元件之间的输出节点（F）的分压器。 当反熔丝装置处于其未编程状态时，偏置元件和反熔丝元件中的每一个都是不导电的。 当反熔丝装置处于其编程状态时，偏置元件保持不导电，但是反熔丝元件是导电的。 反熔丝元件在其未编程状态和编程状态之间的电阻差异导致当在反熔断器件上施加1V的电压时，在输出节点处看到的电压差为几百微升。 该电压差非常高，可以使用简单的感测电路容易地感测。

    Stabilized direct sensing memory architecture
    9.
    发明专利
    Stabilized direct sensing memory architecture 有权
    稳定的直接感知存储器架构

    公开(公告)号：JP2003037491A

    公开(公告)日：2003-02-07

    申请号：JP2002136924

    申请日：2002-05-13

    Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーション

    Inventor： FIFIELD JOHN A ,  STORASKA DANIEL W ,  WIN K RUK

    IPC: H03K19/0175 ,  G11C7/06 ,  G11C11/409 ,  H03K19/0944

    CPC classification number: G11C7/04 ,  G11C7/067

    Abstract: PROBLEM TO BE SOLVED: To provide a stabilized direct sensing memory architecture which provides Process, Voltage and Temperature(PVT) compensation in a memory array to a direct sense circuit to increase the manufacturing yield thereof, and to extend the operating voltage and temperature ranges thereof independent of manufacturing tolerances. SOLUTION: A single-ended sense amplifier structure has a common source NFET amplifier with an adjustable current source load provided by a PFET. The PFET current source is automatically adjusted to place the NFET amplifier in an operating range to provide maximum amplification of a small signal, superimposed on a bitline precharge voltage. A simulating bias generator circuit provides this operating point adjustment, and realizes a direct, single-ended sensing operation using a small number of transistors.

    Abstract translation: 要解决的问题：提供一种稳定的直接感测存储器架构，其将存储器阵列中的过程，电压和温度（PVT）补偿提供给直接感测电路以增加其制造产量，并且延长其工作电压和温度范围 独立于制造公差。 解决方案：单端读出放大器结构具有公共源极NFET放大器，具有由PFET提供的可调电流源负载。 自动调节PFET电流源，使NFET放大器工作在一个工作范围内，以提供叠加在位线预充电电压上的小信号的最大放大。 模拟偏置发生器电路提供该工作点调整，并且使用少量晶体管实现直接的单端感测操作。

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