公开(公告)号：DE10310571A1

公开(公告)日：2003-10-02

申请号：DE10310571

申请日：2003-03-11

Applicant: INFINEON TECHNOLOGIES AG ,  IBM

Inventor： CHIDAMBARRAO DURESETI ,  DIVAKARUNI RAMACHANDRA ,  MANDELMAN JACK A ,  MCSTAV KEVIN

IPC: H01L21/8242 ,  H01L29/10 ,  H01L29/78 ,  H01L27/108

Abstract: Short channel effects in vertical MOSFET transistors are considerably reduced, junction leakage in DRAM cells is reduced and other device parameters are unaffected in a transistor having a vertically asymmetric threshold implant. A preferred embodiment has the peak of the threshold implant moved from the conventional location of midway between source and drain to a point no more than one third of the channel length below the bottom of the source.