公开(公告)号：DE10361272A1

公开(公告)日：2004-08-05

申请号：DE10361272

申请日：2003-12-24

Applicant: IBM ,  INFINEON TECHNOLOGIES AG

Inventor： CHIDAMBARRAO DURESETI ,  DIVAKARUNI RAMACHANDRA ,  MANDELMAN JACK A ,  VAN ROIJEN RAYMOND

IPC: H01L21/8242

Abstract: A DRAM cell with a vertical transistor forms a buried strap outdiffusion with reduced lateral extent by shifting high temperature steps that affect the thermal budget before the initial buried strap diffusion. The gate conductor is formed in two steps, with poly sidewalls being put down above a sacrificial Trench top oxide to form a self-aligned poly-gate insulator structure before the formation of the LDD extension.

公开(公告)号：DE10344862A1

公开(公告)日：2004-04-15

申请号：DE10344862

申请日：2003-09-26

Applicant: INFINEON TECHNOLOGIES AG ,  IBM

Inventor： DIVAKARUNI RAMACHANDRA ,  FEHLAUER GERD T ,  KUDELKA STEPHAN ,  MANDELMAN JACK A ,  SCHROEDER UWE ,  TEWS HELMUT

IPC: H01L21/334 ,  H01L21/8242 ,  H01L27/108 ,  H01L29/94

Abstract: A trench capacitor memory cell structure is provided with includes a vertical collar region that suppresses current leakage of an adjacent vertical parasitic transistor that exists between the vertical MOSFET and the underlying trench capacitor. The vertical collar isolation, which has a vertical length of about 0.50 mum or less, includes a first portion that is present partially outside the trench and a second portion that is present inside the trench. The first portion of the collar oxide is thicker than said second portion oxide thereby reducing parasitic current leakage.

公开(公告)号：DE10310571A1

公开(公告)日：2003-10-02

申请号：DE10310571

申请日：2003-03-11

Applicant: INFINEON TECHNOLOGIES AG ,  IBM

Inventor： CHIDAMBARRAO DURESETI ,  DIVAKARUNI RAMACHANDRA ,  MANDELMAN JACK A ,  MCSTAV KEVIN

IPC: H01L21/8242 ,  H01L29/10 ,  H01L29/78 ,  H01L27/108

Abstract: Short channel effects in vertical MOSFET transistors are considerably reduced, junction leakage in DRAM cells is reduced and other device parameters are unaffected in a transistor having a vertically asymmetric threshold implant. A preferred embodiment has the peak of the threshold implant moved from the conventional location of midway between source and drain to a point no more than one third of the channel length below the bottom of the source.

公开(公告)号：DE69705443T2

公开(公告)日：2002-05-16

申请号：DE69705443

申请日：1997-02-13

Applicant: IBM ,  INFINEON TECHNOLOGIES AG

Inventor： STENGL REINHARD J ,  HAMMERL ERWIN ,  MANDELMAN JACK A ,  HO HERBERT L ,  SRINIVASAN RADHIKA ,  SHORT ALVIN P

IPC: H01L27/00 ,  H01L21/822 ,  H01L21/8242 ,  H01L27/04 ,  H01L27/108

Abstract: In a method for making an electrical connection between a trench storage capacitor and an access transistor in a DRAM cell, the electrical connection (90) is formed through the selectively controlled outdiffusion of either N-type or P-type dopants present in the trench through a single crystalline semiconducting material (60) which is grown by epitaxy (epi) from the trench sidewall. This epitaxially grown single crystalline layer acts as a barrier to excessive dopant outdiffusion which can occur in the processing of conventional DRAMs.

公开(公告)号：DE69705443D1

公开(公告)日：2001-08-09

申请号：DE69705443

申请日：1997-02-13

Applicant: IBM ,  INFINEON TECHNOLOGIES AG

Inventor： STENGL REINHARD J ,  HAMMERL ERWIN ,  MANDELMAN JACK A ,  HO HERBERT L ,  SRINIVASAN RADHIKA ,  SHORT ALVIN P

IPC: H01L27/00 ,  H01L21/822 ,  H01L21/8242 ,  H01L27/04 ,  H01L27/108

Abstract: In a method for making an electrical connection between a trench storage capacitor and an access transistor in a DRAM cell, the electrical connection (90) is formed through the selectively controlled outdiffusion of either N-type or P-type dopants present in the trench through a single crystalline semiconducting material (60) which is grown by epitaxy (epi) from the trench sidewall. This epitaxially grown single crystalline layer acts as a barrier to excessive dopant outdiffusion which can occur in the processing of conventional DRAMs.

公开(公告)号：DE10350703A1

公开(公告)日：2004-05-27

申请号：DE10350703

申请日：2003-10-30

Applicant: IBM ,  INFINEON TECHNOLOGIES AG

Inventor： MANDELMAN JACK A ,  CHUDZIK MICHAEL ,  SEITZ MIHEL

IPC: H01L27/108 ,  H01L21/329 ,  H01L21/8242 ,  H01L29/94

Abstract: A memory cell includes: a trench capacitor, including a trench silicon layer having an upper portion and a lower portion, and a buried plate disposed adjacent the lower portion of the trench silicon layer; an array FET having a gate portion, a drain portion, a source portion, and a buried strap coupled to one of the source and drain portions, the buried strap being in communication with the upper portion of the trench silicon layer; and a collar disposed about the upper portion of the trench silicon layer and between the buried strap and the buried plate, the collar including a re-entrant bend that is operable to decrease an electric field between the buried strap and the buried plate.

公开(公告)号：DE69822775T2

公开(公告)日：2005-02-10

申请号：DE69822775

申请日：1998-12-23

Applicant: INFINEON TECHNOLOGIES AG ,  IBM

Inventor： HOENIGSCHMID HEINZ ,  MANDELMAN JACK A ,  KLEINHENZ RICHARD L

IPC: G11C11/408 ,  G11C5/14 ,  G11C11/403 ,  G11C11/4074 ,  G11C11/407

Abstract: Reduced current consumption in a DRAM during standby mode is achieved by switching off the power source that is connected to, for example, the n-well.

公开(公告)号：DE10310569A1

公开(公告)日：2003-10-02

申请号：DE10310569

申请日：2003-03-11

Applicant: INFINEON TECHNOLOGIES AG ,  IBM

Inventor： CHIDAMBARRAO DURESETI ,  LEE KIL-HO ,  MANDELMAN JACK A ,  MCSTAY KEVIN ,  RENGARAJAN RAJESH

IPC: H01L21/265 ,  H01L21/336 ,  H01L21/8242 ,  H01L27/108 ,  H01L29/76 ,  H01L29/78 ,  H01L29/94 ,  H01L31/119

Abstract: Body effects in vertical MOSFET transistors are considerably reduced and other device parameters are unaffected in a vertical transistor having a threshold implant with a peak at the gate and an implant concentration distribution that declines rapidly away from the gate to a plateau having a low p-well concentration value. A preferred embodiment employs two body implants-an angled implant having a peak at the gate that sets the Vt and a laterally uniform low dose implant that sets the well dopant concentration.

公开(公告)号：DE10344862B4

公开(公告)日：2007-12-20

申请号：DE10344862

申请日：2003-09-26

Applicant: INFINEON TECHNOLOGIES AG ,  IBM

Inventor： DIVAKARUNI RAMACHANDRA ,  FEHLAUER GERD T ,  KUDELKA STEPHAN ,  MANDELMAN JACK A ,  SCHROEDER UWE ,  TEWS HELMUT

IPC: H01L27/108 ,  H01L21/334 ,  H01L21/8242 ,  H01L29/94

Abstract: A trench capacitor memory cell structure is provided with includes a vertical collar region that suppresses current leakage of an adjacent vertical parasitic transistor that exists between the vertical MOSFET and the underlying trench capacitor. The vertical collar isolation, which has a vertical length of about 0.50 mum or less, includes a first portion that is present partially outside the trench and a second portion that is present inside the trench. The first portion of the collar oxide is thicker than said second portion oxide thereby reducing parasitic current leakage.

公开(公告)号：DE69822775D1

公开(公告)日：2004-05-06

申请号：DE69822775

申请日：1998-12-23

Applicant: INFINEON TECHNOLOGIES AG ,  IBM

Inventor： HOENIGSCHMID HEINZ ,  MANDELMAN JACK A ,  KLEINHENZ RICHARD L

IPC: G11C11/408 ,  G11C5/14 ,  G11C11/403 ,  G11C11/4074 ,  G11C11/407

Abstract: Reduced current consumption in a DRAM during standby mode is achieved by switching off the power source that is connected to, for example, the n-well.