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公开(公告)号：JP2001024778A
公开(公告)日：2001-01-26
申请号：JP2000140405
申请日：2000-05-12
Applicant: INFINEON TECHNOLOGIES CORP
Inventor： KLINDWORTH ANDRE , HOGL ERIK , FIEDLER ULRICH
Abstract: PROBLEM TO BE SOLVED: To obtain an echo canceller and a method, capable of speedily detecting the existence of a periodic signal and optimized for fast convergence of a filter coefficient by sampling a communication signal incoming during an evaluating time, deciding the counting value of the number of samples having a value within a counting interval and detecting whether the incoming communication signal is a voice signal or the periodic signal. SOLUTION: The maximum amplitude restricting value which can be constituted is set and the amplitude restricting lower value is set so that a counting interval is decided between the lower value and the maximum amplitude restricted value. Then, a communication signal incoming during an evaluating time is sampled, the counting value of the number of samples having a value within the counting interval is decided and whether the incoming communication signal is a voice signal or a periodic signal is detected. For example, in a telephone system 29, an echo canceller 30a operates so as to filter-remove the voice of a far-end speaking person 22 reflected from a hybrid 28a and an echo chanceller 30b operates, so as to filter- remove the voice of a near end speaking person 20 reflected from a hybrid 28b.
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公开(公告)号：JP2000216712A
公开(公告)日：2000-08-04
申请号：JP34084299
申请日：1999-11-30
Applicant: INFINEON TECHNOLOGIES CORP
Inventor： HOGL ERIK , FIEDLER ULRICH
Abstract: PROBLEM TO BE SOLVED: To flexibly convert dissimilar companding rule telephone signals to be transmittable and to improve flexibility by individually controlling a companding rule of a channel of a programmable compression encoder/decoder. SOLUTION: Compression encoder/decoders (hereafter referred to as converters) 104, 108, 114 and 116 independently make a companding rule selectable by a register 130 including a pointer for a look-up table. A received signal from a near end is separated to a multiplexer 102 and inputted to the converter 104, and a companding rule to be used in each channel is selected according to a command from a controller and added to a converter 108 via an echo canceler 106. A program selecting an individual companding rule again is applied to each channel, and the each channel is multiplexed by a multiplexer 110 and transmitted to a target destination. Also, when a signal is received from a far end, it is similarly transmitted in a prescribed format to a near side subscriber by the converter 114, the canceler 106 and the converter 116.
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Patent Agency Ranking
公开(公告)号：JP2000354029A
公开(公告)日：2000-12-19
申请号：JP2000094511
申请日：2000-03-30
Applicant: INFINEON TECHNOLOGIES CORP
Inventor： HOGL ERIK , FIEDLER ULRICH
Abstract: PROBLEM TO BE SOLVED: To minimize a board space and to obtain a stable synchronous signal of high quality by generating a synchronous signal which marks a prescribed side edge for an internal clock having its phase matched with that of an external system clock. SOLUTION: An external system clock is supplied to a subsystem called a 'master' 24 among plural subsystems 22. The master 24 includes a voltage- controlled oscillator(VCO), which has the frequency equal to a multiple of the external system clock and generates a VCO clock signal, having its frequency matched with that of the external system clock. An internal system clock is generated in the master 24 and has the frequency which is equal to that of the external system clock and is matched with the phase of the VCO clock signal. Then the master 24 generates a synchronous signal which marks a prescribed side edge of the internal clock signal. The VCO clock signal, which functions to secure the synchronization of all subsystems 22, is supplied to every subsystem 22 so as to make these clock signals arrive at the same phase.
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公开(公告)号：DE10014477A1
公开(公告)日：2000-12-28
申请号：DE10014477
申请日：2000-03-23
Applicant: INFINEON TECHNOLOGIES CORP SAN
Inventor： HOGL ERIK , FIEDLER ULRICH
IPC: G06F1/10 , G06F1/12 , H03K5/00 , H03L7/06 , H03L7/08 , H04J3/06 , H04L7/00 , H04L7/033 , H04L12/64
Abstract: The circuit for synchronizing multiple sub-systems uses one voltage-controlled oscillator. A phase and frequency aligned signal output from the voltage-controlled oscillator is transmitted to each sub-system within the digital system. The circuit for generating a synchronous clock generates a synchronization signal in a master device that is then supplied as an input to one or more slave devices. The synchronization signal provides a mechanism by which the slave devices achieve identical and simultaneous phase alignments to the internally generated clock in the master device. Independent claims are included for; a method for synchronizing multiple sub-systems using a single voltage-controlled oscillator.
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公开(公告)号：GB2348555A
公开(公告)日：2000-10-04
申请号：GB0004698
申请日：2000-02-28
Applicant: INFINEON TECHNOLOGIES CORP
Inventor： HOGL ERIC , FIEDLER ULRICH
IPC: G06F1/10 , G06F1/12 , H03K5/00 , H03L7/06 , H03L7/08 , H04J3/06 , H04L7/00 , H04L7/033 , H03L7/07 , G06F1/06
Abstract: A method for synchronizing multiple subsystems using one voltage-controlled oscillator includes transmitting a phase and frequency aligned output of a voltage-controlled oscillator to each subsystem within a digital system. A first subsystem 24 of the multiple subsystems generates a first internal clock and outputs a synchronization signal SYNCO to each of the other subsystems. The synchronization signal has a marker that defines a known point in time of the first internal clock. The other subsystems 26 sample the synchronization signal using the output signal of the voltage controller oscillator to determine a starting indicator that indicates the known point in time of the first internal clock. Upon detection of the marker in the synchronization signs the other subsystems starts a second internal clock that is synchronized with the first internal clock. The first subsystem 24 includes a frequency divider 1/M, a phase detector XOR and a delay 32.
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