公开(公告)号：JP2000148528A

公开(公告)日：2000-05-30

申请号：JP30895499

申请日：1999-10-29

Applicant: INFINEON TECHNOLOGIES CORP

Inventor： GARREAU OLIVIER

IPC: G06F11/22 ,  G01R31/28 ,  G01R31/3185

Abstract: PROBLEM TO BE SOLVED: To obtain a test device which supports an embedded debugging protocol by providing a programmable switch which forms a test loop between a master controller and a selected integrated circuit. SOLUTION: The programmable switch 204 is connected to a slave target device 206 which includes JTAG-based integrated circuits IC1 to IC4. At least one of the integrated circuits IC1 to IC4 is an on-chip debugging support(OCDS) integrated circuit which has an on-chip debugging circuit. A switch controller 218 included in the master controller 202 sends a switch control signal out and a programmable switch 204 connects one integrated circuit selected out of the ICI to IC4 to a JTAG controller 210. The controller 210 functionally tests, for example, the integrated circuit ICI by using the corresponding JTAG test protocol.

公开(公告)号：GB2344430B

公开(公告)日：2003-05-07

申请号：GB9925586

申请日：1999-10-28

Applicant: INFINEON TECHNOLOGIES CORP

Inventor： GARREAU OLIVIER

IPC: G06F11/22 ,  G01R31/28 ,  G01R31/3185

Abstract: An apparatus capable of testing a plurality of JTAG compliant integrated circuits where at least one of the integrated circuits includes an enhanced embedded debug module is described. The apparatus is capable of selectively testing certain of the integrated circuits located at specified locations. In this way, integrated circuits included in a target device having defective or missing integrated circuits can still be tested. The apparatus also allows access to enhanced JTAG debug protocol within a mixed IC (OCDS and non-OCDS) network.

公开(公告)号：GB2344430A

公开(公告)日：2000-06-07

申请号：GB9925586

申请日：1999-10-28

Applicant: INFINEON TECHNOLOGIES CORP

Inventor： GARREAU OLIVIER

IPC: G06F11/22 ,  G01R31/28 ,  G01R31/3185

Abstract: An apparatus 200 suitable for JTAG testing integrated circuits comprises: a controller 202, a programmable switch 204 and a data bus arranged to conduct JTAG tests on at least one specified integrated circuit from a group of integrated circuits IC1 - IC4. At least one of the integrated circuits IC1 may be an on-chip debug support integrated circuit including an on-chip debug circuit 208. The apparatus can selectively test certain integrated circuits individually or daisy chained at specified locations and in this way it can work around defective and/or missing integrated circuits and/or apply different test protocols to the integrated circuits. The apparatus provides access to integrated circuits which permits JTAG and/or debug testing to be conducted.

公开(公告)号：DE19943941A1

公开(公告)日：2000-05-11

申请号：DE19943941

申请日：1999-09-14

Applicant: INFINEON TECHNOLOGIES CORP SAN

Inventor： GARREAU OLIVIER

IPC: G06F11/22 ,  G01R31/28 ,  G01R31/3185

Abstract: An apparatus capable of testing a plurality of JTAG compliant integrated circuits where at least one of the integrated circuits includes an enhanced embedded debug module is described. The apparatus is capable of selectively testing certain of the integrated circuits located at specified locations. In this way, integrated circuits included in a target device having defective or missing integrated circuits can still be tested. The apparatus also allows access to enhanced JTAG debug protocol within a mixed IC (OCDS and non-OCDS) network.