公开(公告)号：JP2000338197A

公开(公告)日：2000-12-08

申请号：JP2000095079

申请日：2000-03-30

Applicant: INFINEON TECHNOLOGIES CORP

Inventor： GERD FRANKOVSKI ,  TERLETZKI HARTMUD

IPC: G01R31/28 ,  G01R29/027 ,  G01R31/30 ,  G01R31/317 ,  G01R31/3193 ,  H01L21/66

Abstract: PROBLEM TO BE SOLVED: To execute a high resolution test by using an inexpensive tester of comparatively low frequency by mounting a plurality of delay elements capable of being enabled and disabled by pulses from an operation circuit, and the like. SOLUTION: A semiconductor circuit 12 is formed on a single crystalline such as silicon or a substrate 16 (that is, die or chip), and has a plurality of pins 181-18n. These pins 181-18n are connected to a tester 14 through lines 201-20n to be communicated with the tester 14. The tester 14 transmits a signal to the circuit 12, further receives the signal from the circuit 12 and processes the signal. The circuit 12 has an operation circuit 22 and a test circuit 24. The operation circuit 22 generates pulses of very short width. The test circuit 24 has a plurality of delay elements, and these delay elements are enabled and disabled by pulses from the operation circuit 22. By applying this device, the quality of high frequency of the signal of the circuit is measured by a low frequency test device.

公开(公告)号：WO0227934A2

公开(公告)日：2002-04-04

申请号：PCT/US0129191

申请日：2001-09-19

Applicant: INFINEON TECHNOLOGIES CORP

Inventor： TERLETZKI HARTMUD

IPC: H03K19/094 ,  H03K19/0185

CPC classification number: H03K19/09429

Abstract: Level-shifting circuitry having a level-shifting section and an enable/disable section. The level-shifting section is responsive to an input logic signal. The input logic signal has a first voltage level representative of a first logic state and a second voltage level representative of a second logic state. The level-shifting section provides an output logic signal, such output logic signal having a third voltage level representative of the first logic state of the input logic signal. The enable/disable section is responsive to an enable/disable signal for driving the output logic signal to the third voltage level during a disable mode, such third voltage level being greater than the first or second voltage levels.

Abstract translation: 电平移位电路具有电平移位部分和使能/禁止部分。 电平移位部分响应于输入逻辑信号。 输入逻辑信号具有表示第一逻辑状态的第一电压电平和表示第二逻辑状态的第二电压电平。 电平移位部分提供输出逻辑信号，该输出逻辑信号具有表示输入逻辑信号的第一逻辑状态的第三电压电平。 启用/禁用部分响应于在禁用模式期间将输出逻辑信号驱动到第三电压电平的使能/禁止信号，这样的第三电压电平大于第一或第二电压电平。