METHOD FOR FABRICATING VERTICAL TRANSISTOR RENCH CAPACITOR DRAM CELLS
    1.
    发明申请
    METHOD FOR FABRICATING VERTICAL TRANSISTOR RENCH CAPACITOR DRAM CELLS 审中-公开
    用于制造垂直晶体管RENCH电容器DRAM电池的方法

    公开(公告)号:WO0250896A3

    公开(公告)日:2004-01-08

    申请号:PCT/US0145196

    申请日:2001-11-29

    Abstract: A Dynamic Random Access Memory is fabricated in a semiconductor body (12) of a first conductivity type in which there have been formed an array of memory cells which each include a trench capacitor and a vertical Insulated Gate Field Effect Transistor (IGFET). Each IGFET includes first (18) and second (19) output regions of a second opposite conductivity type and a gate (25) which is separated from a surface of the semiconductor body by a gate dielectric layer (21). A gate electrode (40b) connected to the gate (25) is formed using a Damascene process with insulating sidewall spacer regions (36) being formed before the gate electrode (25) is formed. Borderless contacts (56, 560), which are self aligned, are made to the first output regions (18) of each transistor using a Damascene process.

    Abstract translation: 在第一导电类型的半导体本体(12)中制造动态随机存取存储器,其中已经形成了各自包括沟槽电容器和垂直绝缘栅场效应晶体管(IGFET)的存储单元阵列。 每个IGFET包括第二相对导电类型的第一(18)和第二(19)输出区和通过栅介质层(21)与半导体本体的表面分离的栅极(25)。 连接到栅极(25)的栅电极(40b)使用具有在形成栅电极(25)之前形成的绝缘侧壁间隔区(36)的镶嵌工艺形成。 使用大马士革过程对每个晶体管的第一输出区域(18)进行自对准的无边界触点(56,560)。

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