Abstract:
A Dynamic Random Access Memory is fabricated in a semiconductor body (12) of a first conductivity type in which there have been formed an array of memory cells which each include a trench capacitor and a vertical Insulated Gate Field Effect Transistor (IGFET). Each IGFET includes first (18) and second (19) output regions of a second opposite conductivity type and a gate (25) which is separated from a surface of the semiconductor body by a gate dielectric layer (21). A gate electrode (40b) connected to the gate (25) is formed using a Damascene process with insulating sidewall spacer regions (36) being formed before the gate electrode (25) is formed. Borderless contacts (56, 560), which are self aligned, are made to the first output regions (18) of each transistor using a Damascene process.